{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":1,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":14,"n_cols":5,"rows_kept":14,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[3,2,3,3],[5,2,5,3],[6,2,6,3],[7,2,7,3],[8,2,8,3],[9,2,9,3],[12,2,12,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNINA9910140952703321"]
[null,null,"Titolo",null,"2011 IEEE 29th VLSI Test Symposium"]
[null,null,"Pubbl/distr/stampa",null,"[Place of publication not identified], : IEEE, 2011"]
[null,null,"ISBN",null,"9781612846569"]
[{"$nulls":4},"1612846564"]
[null,null,"Descrizione fisica",null,"1 online resource (328 pages) : illustrations"]
[null,null,"Disciplina",null,"621"]
[null,null,"Soggetti",null,"Integrated circuits - Very large scale integration - Testing"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Bibliographic Level Mode of Issuance: Monograph"]
[null,null,"Nota di contenuto",null,"Foreword -- Organizing Committee -- Program Committee -- Steering Committee -- Reviewers -- Acknowledgements -- Test Technology Technical Council (TTTC) -- Test Technology Educational Program (TTEP) Tutorials -- Awards -- Session 1 Session 1A: Post-Silicon Debug & Customer returns -- Session 1B: 3D ICS -- IP Session 1C: Test and Characterization of High-Speed Circuits -- Session 2 Session 2A: Power Issues in Test -- Session 2B: Analog, Mixed-Signal & RF Test/Diagnosis -- IP Session 2C: On Chip Parametric Sensors -- Session 3 Session 3A: Delay & Performance Test 1 -- Special Session 3B: Hot Topic: Multifaceted Approaches for Field Reliability -- IP Session 3C: Advanced Methods for Leveraging New Test Standards -- Session 4 Special Session 4A: New Topics -- Session 4B: Panel: Security -- IP Session 4C: The Buck Stops With Wafer Test: Dream Or Reality? -- Session 5 Special Session 5A: Apprentice, Season 4 -- Special Session 5B: Panel: How Much Toggle Activity Should We Be Testing With? -- Session 6 Session 6A: Delay & Performance Test 2 -- Session 6B: Memory Test and Repair -- IP Session 6C: The Bang For The Buck With Resiliency: Yield Or Field? -- Session 7 Session 7A: Low-Power IC Test -- Session 7B: On-line & System Testing -- Session 8 Session 8A: Aging, Transients & Soft Errors -- Special Session 8B: New Topic: Solar Cells -- Sessions 9 Special Session 9C: Panel: Coverage Closure in SoC Verification: Are We Chasing a Mirage? -- Session 10 Session 10A: Design for Testability 1 -- Session 10B: Error & Fault Tolerance 1 -- Session 11 Session 11A: Design for Testability 2 -- Session 11B: Error & Fault Tolerance 2 -- Session 12 Session 12A: ATPG & Compression -- Session 12B: Reducing Test & Diagnosis Costs -- Session 13 Special Session 13A: "]
[{"$nulls":4},"Practical Signal Processing at Mixed Signal Test Venues - Trend Removal, Noise Reduction, Wideband Signal Capturing -- Session 13B: Hot Topic: Smart Silicon -- Session 13C: Hot Topic: Design and Test of 3D and Emerging Memories."]