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[null,"1.","Record Nr.",null,"UNISALENTO991002129979707536"]
[null,null,"Titolo",null,"La nuova legge bancaria : il T.U. delle leggi sulla intermediazione bancaria e creditizia e le disposizioni di attuazione : commentario / a cura di Paolo Ferro-Luzzi e Giovanni Castaldi"]
[null,null,"Pubbl/distr/stampa",null,"Milano : A. Giuffrè, 1996-"]
[null,null,"ISBN",null,"8814051615"]
[{"$nulls":4},"8814082200 (v. 5)"]
[null,null,"Descrizione fisica",null,"5 v. ; 25 cm"]
[null,null,"Classificazione",null,"CM-XVI/A"]
[null,null,"Disciplina",null,"341.7511"]
[{"$nulls":4},"346.45082"]
[null,null,"Soggetti",null,"Banche - Direttive della CEE - Attuazione"]
[{"$nulls":4},"Banche - Legislazione"]
[null,null,"Lingua di pubblicazione",null,"Italiano"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,"Nota di contenuto",null,"4.: Appendice di aggiornamento / Alessandro Napolitano. - xiv, 221 p."]
[{"$nulls":4},"5.: Seconda appendice di aggiornamento / Alessandro Napolitano. - xxii, 471 p."]
[null,"2.","Record Nr.",null,"UNINA9910139802703321"]
[null,null,"Autore",null,"Voldman Steven H"]
[null,null,"Titolo",null,"ESD [[electronic resource] ] : failure mechanisms and models / / Steven H. Voldman"]
[null,null,"Pubbl/distr/stampa",null,"Chichester, West Sussex, U.K. ; ; Hoboken, NJ, : J. Wiley, 2009"]
[null,null,"ISBN",null,"1-282-23713-6"]
[{"$nulls":4},"9786612237133"]
[{"$nulls":4},"0-470-74725-0"]
[{"$nulls":4},"0-470-74726-9"]
[null,null,"Descrizione fisica",null,"1 online resource (410 p.)"]
[null,null,"Disciplina",null,"621.381"]
[null,null,"Soggetti",null,"Semiconductors - Failures"]
[{"$nulls":4},"Integrated circuits - Protection"]
[{"$nulls":4},"Integrated circuits - Testing"]
[{"$nulls":4},"Integrated circuits - Reliability"]
[{"$nulls":4},"Electric discharges"]
[{"$nulls":4},"Electrostatics"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"ESD Failure Mechanisms and Models; Contents; About the Author; Preface; Acknowledgments; 1 Failure Analysis and ESD; 1.1 INTRODUCTION; 1.1.1 FA Techniques for Evaluation of ESD Events; 1.1.2 Fundamental Concepts of ESD FA Methods and Practices; 1.1.3 ESD Failure: Why Do Semiconductor Chips Fail?; 1.1.4 How to Use FA to Design ESD Robust Technologies; 1.1.5 How to Use FA to Design ESD Robust Circuits; 1.1.6 How to Use FA for Temperature Prediction; 1.1.7 How to Use Failure Models for Power Prediction; 1.1.8 FA Methods, Design Rules, and ESD Ground Rules"]
[{"$nulls":4},"1.1.9 FA and Semiconductor Process-Induced ESD Design Asymmetry 1.1.10 FA Methodology and Electro-thermal Simulation; 1.1.11 FA and ESD Testing Methodology; 1.1.12 FA Methodology for Evaluation of ESD Parasitics; 1.1.13 FA Methods and ESD Device Operation Verification; 1.1.14 FA Methodology to Evaluate Inter-power Rail Electrical Connectivity; 1.1.15 How to Use FA to Eliminate Failure Mechanisms; 1.2 ESD FAILURE: HOW DO MICRO-ELECTRONIC DEVICES FAIL?; 1.2.1 ESD Failure: How Do Metallurgical Junctions Fail?; 1.2.2 ESD Failure: "]
[{"$nulls":4},"How Do Insulators Fail?; 1.2.3 ESD Failure: How Do Metals Fail?"]
[{"$nulls":4},"1.3 SENSITIVITY OF SEMICONDUCTOR COMPONENTS 1.3.1 ESD Sensitivity as a Function of Materials; 1.3.2 ESD Sensitivity as a Function of Semiconductor Devices; 1.3.3 ESD Sensitivity as a Function of Product Type; 1.3.4 ESD and Technology Scaling; 1.3.5 ESD Technology Roadmap; 1.4 HOW DO SEMICONDUCTOR CHIPS FAIL--ARE THE FAILURES RANDOM OR SYSTEMATIC?; 1.5 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 2 Failure Analysis Tools, Models, and Physics of Failure; 2.1 FA TECHNIQUES FOR EVALUATION OF ESD EVENTS; 2.2 FA TOOLS; 2.2.1 Optical Microscope; 2.2.2 Scanning Electron Microscope"]
[{"$nulls":4},"2.2.3 Transmission Electron Microscope 2.2.4 Emission Microscope; 2.2.5 Thermally Induced Voltage Alteration; 2.2.6 Superconducting Quantum Interference Device Microscope; 2.2.7 Atomic Force Microscope; 2.2.8 The 2-D AFM; 2.2.9 Picosecond Current Analysis Tool; 2.2.10 Transmission Line Pulse--Pico second Current Analysis Tool; 2.3 ESD SIMULATION: ESD PULSE MODELS; 2.3.1 Human Body Model; 2.3.2 Machine Model; 2.3.3 Cassette Model; 2.3.4 Socketed Device Model; 2.3.5 Charged Board Model; 2.3.6 Cable Discharge Event; 2.3.7 IEC System-Level Pulse Model; 2.3.8 Human Metal Model"]
[{"$nulls":4},"2.3.9 Transmission Line Pulse Testing 2.3.10 Very Fast Transmission Line Pulse (VF-TLP) Model; 2.3.11 Ultra-fast Transmission Line Pulse (UF-TLP) Model; 2.4 ELECTRO-THERMAL PHYSICAL MODELS; 2.4.1 Tasca Model; 2.4.2 Wunsch-Bell Model; 2.4.3 Smith-Littau Model; 2.4.4 Ash Model; 2.4.5 Arkihpov, Astvatsaturyan, Godovosyn, and Rudenko Model; 2.4.6 Dwyer, Franklin, and Campbell Model; 2.4.7 Vlasov-Sinkevitch Model; 2.5 STATISTICAL MODELS FOR ESD PREDICTION; 2.6 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 3 CMOS Failure Mechanisms; 3.1 TABLES OF CMOS ESD FAILURE MECHANISMS"]
[{"$nulls":4},"3.2 LOCOS ISOLATION-DEFINED CMOS"]
[null,null,null,"Sommario/riassunto","Electrostatic discharge (ESD) failure mechanisms continue to impact semiconductor components and systems as technologies scale from micro- to nano-electronics. This book studies electrical overstress, ESD, and latchup from a failure analysis and case-study approach. It provides a clear insight into the physics of failure from a generalist perspective, followed by investigation of failure mechanisms in specific technologies, circuits, and systems. The book is unique in covering both the failure mechanism and the practical solutions to fix the problem from either a technology or circuit method"]