{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":2,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":49,"n_cols":5,"rows_kept":49,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[2,4,2,5],[3,2,3,3],[4,2,4,3],[8,2,8,3],[9,2,9,3],[10,2,10,3],[11,2,11,3],[12,2,12,3],[13,2,13,3],[17,2,17,3],[18,2,18,3],[22,2,22,3],[30,2,30,3],[30,4,30,5],[31,2,31,3],[31,4,31,5],[32,2,32,3],[32,4,32,5],[33,2,33,3],[34,2,34,3],[37,2,37,3],[38,2,38,3],[39,2,39,3],[42,2,42,3],[43,2,43,3],[47,2,47,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNINA9910131049403321"]
[null,null,"Autore",null,"Voldman Steven H"]
[null,null,"Titolo",null,"ESD [[electronic resource] ] : design and synthesis / / Steven H. Voldman"]
[null,null,"Pubbl/distr/stampa",null,"Chichester, West Sussex, U.K., : Wiley, 2011"]
[null,null,"ISBN",null,"1-283-40527-X"]
[{"$nulls":4},"9786613405272"]
[{"$nulls":4},"1-119-99114-5"]
[{"$nulls":4},"1-119-99113-7"]
[null,null,"Edizione",null,"[1st edition]"]
[null,null,"Descrizione fisica",null,"1 online resource (292 p.)"]
[null,null,"Collana",null,"ESD series"]
[null,null,"Classificazione",null,"TEC008010"]
[null,null,"Disciplina",null,"621.3815/2"]
[null,null,"Soggetti",null,"Semiconductors - Protection"]
[{"$nulls":4},"Integrated circuits - Protection"]
[{"$nulls":4},"Electrostatics"]
[{"$nulls":4},"Analog electronic systems - Design and construction"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"ESD Design and Synthesis; Contents; About the Author; Preface; Acknowledgments; 1 ESD Design Synthesis; 1.1 ESD DESIGN SYNTHESIS AND ARCHITECTURE FLOW; 1.1.1 Top-Down ESD Design; 1.1.2 Bottom-Up ESD Design; 1.1.3 Top-Down ESD Design - Memory Semiconductor Chips; 1.1.4 Top-Down ESD Design - ASIC Design System; 1.2 ESD DESIGN - THE SIGNAL PATH AND THE ALTERNATE CURRENT PATH; 1.3 ESD ELECTRICAL CIRCUIT AND SCHEMATIC ARCHITECTURE CONCEPTS; 1.3.1 The Ideal ESD Network and the Current-Voltage DC Design Window; 1.3.2 The ESD Design Window"]
[{"$nulls":4},"1.3.3 The Ideal ESD Networks in the Frequency Domain Design Window1.4 MAPPING SEMICONDUCTOR CHIPS AND ESD DESIGNS; 1.4.1 Mapping Across Semiconductor Fabricators; 1.4.2 ESD Design Mapping Across Technology Generations; 1.4.3 Mapping from Bipolar Technology to CMOS Technology; 1.4.4 Mapping from Digital CMOS Technology to Mixed Signal Analog-Digital CMOS Technology; 1.4.5 Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI); 1.4.6 ESD Design - Mapping CMOS to RF CMOS Technology; 1.5 ESD CHIP ARCHITECTURE, AND ESD TEST STANDARDS; 1.5.1 ESD Chip Architecture and ESD Testing"]
[{"$nulls":4},"1.6 ESD TESTING1.6.1 ESD Qualification Testing; 1.6.2 ESD Test Models; "]
[{"$nulls":4},"1.6.3 ESD Characterization Testing; 1.6.4 TLP Testing; 1.7 ESD CHIP ARCHITECTURE AND ESD ALTERNATIVE CURRENT PATHS; 1.7.1 ESD Circuits, I/O, and Cores; 1.7.2 ESD Signal Pin Circuits; 1.7.3 ESD Power Clamp Networks; 1.7.4 ESD Rail-to-Rail Circuits; 1.7.5 ESD Design and Noise; 1.7.6 Internal Signal Path ESD Networks; 1.7.7 Cross-Domain ESD Networks; 1.8 ESD NETWORKS, SEQUENCING, AND CHIP ARCHITECTURE; 1.9 ESD DESIGN SYNTHESIS - LATCHUP-FREE ESD NETWORKS; 1.10 ESD DESIGN CONCEPTS - BUFFERING - INTER-DEVICE"]
[{"$nulls":4},"1.11 ESD DESIGN CONCEPTS - BALLASTING - INTER-DEVICE1.12 ESD DESIGN CONCEPTS - BALLASTING - INTRA-DEVICE; 1.13 ESD DESIGN CONCEPTS - DISTRIBUTED LOAD TECHNIQUES; 1.14 ESD DESIGN CONCEPTS - DUMMY CIRCUITS; 1.15 ESD DESIGN CONCEPTS - POWER SUPPLY DE-COUPLING; 1.16 ESD DESIGN CONCEPTS - FEEDBACK LOOP DE-COUPLING; 1.17 ESD LAYOUT AND FLOORPLAN-RELATED CONCEPTS; 1.17.1 Design Symmetry; 1.17.2 Design Segmentation; 1.17.3 ESD Design Concepts - Utilization of Empty Space; 1.17.4 ESD Design Synthesis - Across Chip Line Width Variation (ACLV); 1.17.5 ESD Design Concepts - Dummy Shapes"]
[{"$nulls":4},"1.17.6 ESD Design Concepts - Dummy Masks1.17.7 ESD Design Concepts - Adjacency; 1.18 ESD DESIGN CONCEPTS - ANALOG CIRCUIT TECHNIQUES; 1.19 ESD DESIGN CONCEPTS - WIRE BONDS; 1.20 DESIGN RULES; 1.20.1 ESD Design Rule Checking (DRC); 1.20.2 ESD Layout vs. Schematic (LVS); 1.20.3 Electrical Resistance Checking (ERC); 1.21 SUMMARY AND CLOSING COMMENTS; PROBLEMS; REFERENCES; 2 ESD Architecture and Floorplanning; 2.1 ESD DESIGN FLOORPLAN; 2.2 PERIPHERAL I/O DESIGN; 2.2.1 Pad-Limited Peripheral I/O Design Architecture; 2.2.2 Pad-Limited Peripheral I/O Design Architecture - Staggered I/O"]
[{"$nulls":4},"2.2.3 Core-Limited Peripheral I/O Design Architecture"]
[null,null,null,"Sommario/riassunto","Electrostatic discharge (ESD) continues to impact semiconductor components and systems as technologies scale from micro- to nano-electronics. This book studies electrical overstress, ESD, and latchup from a whole-chip ESD design synthesis approach. It provides a clear insight into the integration of ESD protection networks from a generalist perspective, followed by examples in specific technologies, circuits, and chips. Uniquely both the semiconductor chip integration issues and floorplanning of ESD networks are covered from a 'top-down' design approach. Look inside for extensive coverage"]
[null,"2.","Record Nr.",null,"UNINA9910783447203321"]
[null,null,"Autore",null,"Tomasko Robert M"]
[null,null,"Titolo",null,"Bigger isn't always better [[electronic resource] ] : the new mindset for real business growth / / Robert M. Tomasko"]
[null,null,"Pubbl/distr/stampa",null,"New York, : AMACOM, c2006"]
[null,null,"ISBN",null,"1-281-12643-8"]
[{"$nulls":4},"9786611126438"]
[{"$nulls":4},"0-8144-2903-3"]
[null,null,"Descrizione fisica",null,"1 online resource (272 p.)"]
[null,null,"Disciplina",null,"658.4/06"]
[null,null,"Soggetti",null,"Corporations - Growth"]
[{"$nulls":4},"Sustainable development"]
[{"$nulls":4},"Creative ability in business"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references (p. 239-252) and index."]
[null,null,"Nota di contenuto",null,"Is bigger better? -- A bigger stock price is not always a good thing -- Growth is about moving forward -- Are you a fixer or a grower? -- Know where to look -- Know what they want -- Tell the truth -- Create tension to generate forward movement -- Win hearts and minds -- Master momentum and bounce -- Know when to let go, and how to share the wealth."]
[null,null,null,"Sommario/riassunto","When it comes to business growth, bigger is not always better. The key to achieving growth is to change the way we think about it. Genuine growth has more to do with reaching maximum potential than reaching maximum size. Based on ten years of research and dozens of personal interviews by the author, Bigger Isn't Always Better identifies seven key habits of mind that lead to real growth, and shows, through many examples, how they have been applied successfully.Examples include Darcy Williams at Nike, who championed a range of products for women that did not fit into the established marke"]