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[null,"1.","Record Nr.",null,"UNINA9910130802303321"]
[null,null,"Titolo",null,"2012 IEEE 18th International on-Line Testing Symposium"]
[null,null,"Pubbl/distr/stampa",null,"[Place of publication not identified], : IEEE, 2012"]
[null,null,"ISBN",null,"9781467320856"]
[{"$nulls":4},"1467320854"]
[null,null,"Descrizione fisica",null,"1 online resource : illustrations"]
[null,null,"Disciplina",null,"621"]
[null,null,"Soggetti",null,"Electronic circuit design"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Bibliographic Level Mode of Issuance: Monograph"]
[null,null,null,"Sommario/riassunto","Conventional fault tolerance techniques either require big overheads or have limited reliability. We propose a novel fault tolerant flip-flop (SETTOFF) that addresses timing errors and soft errors in one cost-efficient architecture. In SETTOFF, most SEUs are detected by monitoring the illegal transitions at the output of a flip-flop and recovered by inverting the cell state. SETs, timing errors and the other SEUs are detected by a time redundancy-based architecture. For a 10% activity rate, SETTOFF consumes 35.8% and 39.7% more power than a library flip-flop in 120nm and 65nm technologies, respectively. It only consumes about 5.7% more power than the detection based RazorII flip-flop [1]. SETTOFF therefore provides an increased coverage of fault tolerance with only moderate increase in overhead, hence it is suitable for building highly reliable systems at lower cost than the traditional techniques."]