LEADER 00975cam2 22002653 450 001 SOB006677 005 20121219113223.0 010 $a8813229208 100 $a20040211d2001 |||||ita|0103 ba 101 $aita 102 $aIT 200 1 $a<<26: >>Revocatoria fallimentare e stato di insolvenza$fElisabetta Bertacchini 210 $aPadova$cCEDAM$d2001 215 $aXVI, 226 p.$d24 cm 461 1$1001SOB006679$12001 $aTrattato di diritto commerciale e di diritto pubblico dell'economia / diretto da Francesco Galgano 700 1$aBertacchini$b, Elisabetta$3AF00006774$4070$0236957 801 0$aIT$bUNISOB$c20121219$gRICA 850 $aUNISOB 852 $aUNISOB$j340$m104837 912 $aSOB006677 940 $aM 102 Monografia moderna SBN 941 $aM 957 $a340$b001446$i-26$gSi$d104837$rACQUISTO$1catenacci$2UNISOB$3UNISOB$420080409104411.0$520121219113130.0$6bethb 996 $aRevocatoria fallimentare e stato di insolvenza$9662795 997 $aUNISOB LEADER 05542nam 2200697 a 450 001 9910144431803321 005 20200520144314.0 010 $a1-282-34988-0 010 $a9786612349881 010 $a0-470-98762-6 010 $a0-470-98761-8 035 $a(CKB)1000000000687361 035 $a(EBL)470251 035 $a(SSID)ssj0000297046 035 $a(PQKBManifestationID)11223346 035 $a(PQKBTitleCode)TC0000297046 035 $a(PQKBWorkID)10327263 035 $a(PQKB)10444032 035 $a(Au-PeEL)EBL470251 035 $a(CaPaEBR)ebr10301213 035 $a(CaONFJC)MIL234988 035 $a(CaSebORM)9780470060704 035 $a(MiAaPQ)EBC470251 035 $a(OCoLC)232611436 035 $a(EXLCZ)991000000000687361 100 $a20071023d2008 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aFSM-based digital design using Verilog HDL$b[electronic resource] /$fPeter Minns, Ian Elliott 205 $a1st edition 210 $aChichester, England ;$aHoboken, NJ $cJ. Wiley & Sons$dc2008 215 $a1 online resource (409 p.) 300 $aDescription based upon print version of record. 311 $a0-470-06070-0 320 $aIncludes bibliographical references and index. 327 $aFSM-based Digital Design using Verilog HDL; Contents; Preface; Acknowledgements; 1 Introduction to Finite-State Machines and State Diagrams for the Design of Electronic Circuits and Systems; 1.1 INTRODUCTION; 1.2 LEARNING MATERIAL; 1.3 SUMMARY; 2 Using State Diagrams to Control External Hardware Subsystems; 2.1 INTRODUCTION; 2.2 LEARNING MATERIAL; 2.3 SUMMARY; 3 Synthesizing Hardware from a State Diagram; 3.1 INTRODUCTION TO FINITE-STATE MACHINE SYNTHESIS; 3.2 LEARNING MATERIAL; 3.3 SUMMARY; 4 Synchronous Finite-State Machine Designs; 4.1 TRADITIONAL STATE DIAGRAM SYNTHESIS METHOD 327 $a4.2 DEALING WITH UNUSED STATES4.3 DEVELOPMENT OF A HIGH/LOW ALARM INDICATOR SYSTEM; 4.3.1 Testing the Finite-State Machine using a Test-Bench Module; 4.4 SIMPLE WAVEFORM GENERATOR; 4.4.1 Sampling Frequency and Samples per Waveform; 4.5 THE DICE GAME; 4.5.1 Development of the Equations for the Dice Game; 4.6 BINARY DATA SERIAL TRANSMITTER; 4.6.1 The RE Counter Block in the Shift Register of Figure 4.15; 4.7 DEVELOPMENT OF A SERIAL ASYNCHRONOUS RECEIVER; 4.7.1 Finite-State Machine Equations; 4.8 ADDING PARITY DETECTION TO THE SERIAL RECEIVER SYSTEM; 4.8.1 To Incorporate the Parity 327 $a4.8.2 D-Type Equations for Figure 4.264.9 AN ASYNCHRONOUS SERIAL TRANSMITTER SYSTEM; 4.9.1 Equations for the Asynchronous Serial Transmitter; 4.10 CLOCKED WATCHDOG TIMER; 4.10.1 D Flip-Flop Equations; 4.10.2 Output Equation; 4.11 SUMMARY; 5 The One Hot Technique in Finite-State Machine Design; 5.1 THE ONE HOT TECHNIQUE; 5.2 A DATA ACQUISITION SYSTEM; 5.3 A SHARED MEMORY SYSTEM; 5.4 FAST WAVEFORM SYNTHESIZER; 5.4.1 Specification; 5.4.2 A Possible Solution; 5.4.3 Equations for the d Inputs to D Flip-Flops; 5.4.4 Output Equations 327 $a5.5 CONTROLLING THE FINITE-STATE MACHINE FROM A MICROPROCESSOR/MICROCONTROLLER5.6 A MEMORY-CHIP TESTER; 5.7 COMPARING ONE HOT WITH THE MORE CONVENTIONAL DESIGN METHOD OF CHAPTER 4; 5.8 A DYNAMIC MEMORY ACCESS CONTROLLER; 5.8.1 Flip-Flop Equations; 5.8.2 Output Equations; 5.9 HOW TO CONTROL THE DYNAMIC MEMORY ACCESS FROM A MICROPROCESSOR; 5.10 DETECTING SEQUENTIAL BINARY SEQUENCES USING A FINITE-STATE MACHINE; 5.11 SUMMARY; 6 Introduction to Verilog HDL; 6.1 A BRIEF BACKGROUND TO HARDWARE DESCRIPTION LANGUAGES; 6.2 HARDWARE MODELLING WITH VERILOG HDL: THE MODULE 327 $a6.3 MODULES WITHIN MODULES: CREATING HIERARCHY6.4 VERILOG HDL SIMULATION: A COMPLETE EXAMPLE; REFERENCES; 7 Elements of Verilog HDL; 7.1 BUILT-IN PRIMITIVES AND TYPES; 7.1.1 Verilog Types; 7.1.2 Verilog Logic and Numeric Values; 7.1.3 Specifying Values; 7.1.4 Verilog HDL Primitive Gates; 7.2 OPERATORS AND EXPRESSIONS; 7.3 EXAMPLE ILLUSTRATING THE USE OF VERILOG HDL OPERATORS: HAMMING CODE ENCODER; 7.3.1 Simulating the Hamming Encoder; REFERENCES; 8 Describing Combinational and Sequential Logic using Verilog HDL; 8.1 THE DATA-FLOW STYLE OF DESCRIPTION: REVIEW OF THE CONTINUOUS ASSIGNMENT 327 $a8.2 THE BEHAVIOURAL STYLE OF DESCRIPTION: THE SEQUENTIAL BLOCK 330 $aAs digital circuit elements decrease in physical size, resulting in increasingly complex systems, a basic logic model that can be used in the control and design of a range of semiconductor devices is vital. Finite State Machines (FSM) have numerous advantages; they can be applied to many areas (including motor control, and signal and serial data identification to name a few) and they use less logic than their alternatives, leading to the development of faster digital hardware systems. This clear and logical book presents a range of novel techniques for the rapid and reliable design of digit 606 $aVerilog (Computer hardware description language) 606 $aDigital electronics 606 $aSequential machine theory 615 0$aVerilog (Computer hardware description language) 615 0$aDigital electronics. 615 0$aSequential machine theory. 676 $a004/.33 700 $aMinns$b Peter D$0995482 701 $aElliott$b Ian D$0995483 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910144431803321 996 $aFSM-based digital design using Verilog HDL$92280670 997 $aUNINA LEADER 02211oas 2200685 a 450 001 9910693440403321 005 20251106213014.0 035 $a(OCoLC)459794280 035 $a(CONSER) 2009230392 035 $a(CKB)1000000000808532 035 $a(EXLCZ)991000000000808532 100 $a20091026b20072011 ua a 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aAtlanta High Intensity Drug Trafficking Area drug market analysis 210 1$aJohnstown, PA :$cNational Drug Intelligence Center, U.S. Dept. of Justice,$d2007-2011. 215 $a1 online resource (5 volumes) 300 $aIn scope of the U.S. Government Publishing Office Cataloging and Indexing Program (C&I) and Federal Depository Library Program (FDLP). 311 08$a2152-3282 517 1 $aDrug market analysis. 606 $aDrug control$zGeorgia$zAtlanta Region$vPeriodicals 606 $aFederal aid to law enforcement agencies$zGeorgia$zAtlanta Region$vPeriodicals 606 $aDrug control$2fast$3(OCoLC)fst01032891 606 $aFederal aid to law enforcement agencies$2fast$3(OCoLC)fst00922223 607 $aGeorgia$zAtlanta Region$2fast 608 $aPeriodicals.$2fast 608 $aPeriodicals.$2lcgft 615 0$aDrug control 615 0$aFederal aid to law enforcement agencies 615 7$aDrug control. 615 7$aFederal aid to law enforcement agencies. 676 $a363 712 02$aNational Drug Intelligence Center (U.S.) 712 02$aHigh Intensity Drug Trafficking Area Program (U.S.) 712 02$aUnited States.$bDepartment of Justice. 801 0$bGPO 801 1$bGPO 801 2$bGPO 801 2$bDLC 801 2$bGPO 801 2$bOCLCQ 801 2$bOCLCO 801 2$bOCLCQ 801 2$bOCLCA 801 2$bOCLCQ 801 2$bGILDS 801 2$bOCLCA 801 2$bOCLCF 801 2$bOCLCO 801 2$bOCLCQ 801 2$bGPO 801 2$bOCLCL 801 2$bOCLCQ 906 $aJOURNAL 912 $a9910693440403321 996 $aAtlanta High Intensity Drug Trafficking Area drug market analysis$93203346 997 $aUNINA