LEADER 01269nam0 22003133i 450 
001 USM1619921
005 20240906063500.0
010   $a0471687839
100   $a20101230d2006    ||||0itac50      ba
101 | $aeng
102   $aus
181  1$6z01$ai $bxxxe  
182  1$6z01$an
200 1 $aSynthesis of arithmetic circuits$eFPGA, ASIC and embedded systems$fJean-Pierre Deschamps, Géry Jean Antoine Bioul, Gustavo D. Sutter
210   $aHoboken$cWiley-Interscience$d©2006
215   $aXIX, 556 p.$d25 cm.
606   $aCircuiti logici$2FIR$3NAPC024222$9I
676   $a621.39$9INGEGNERIA DEGLI ELABORATORI$v14
676   $a621.395$9INGEGNERIA DEGLI ELABORATORI. CIRCUITERIA$v22
700  1$aDeschamps$b, Jean-Pierre$f <1945-    >$3MILV191105$4070$029992
701  1$aBioul$b, Géry Jean Antoine$3USMV796111$4070$0739233
701  1$aSutter$b, Gustavo D.$3USMV796112$4070$0772186
801  3$aIT$bIT-NA0079$c20101230
850   $aIT-BN0095          
912   $aUSM1619921
950  0$aBiblioteca Centralizzata di Ateneo$b1 v.$c1 v.$d 01SALA DING 621.39                  DES.sy$e 0102 0000060985    B A4                    1 v.$f3 $h20070110$i20101230
977   $a 01
996   $aSynthesis of arithmetic circuits$91576281
997   $aUNISANNIO