LEADER 01470nam0 22003493i 450 
001 NAP0501640
005 20250110063018.0
010   $a0818621273
100   $a20110111d1991    ||||0itac50      ba
101 | $aeng
102   $aus
181  1$6z01$ai $bxxxe  
182  1$6z01$an
200 1 $aMultiple-valued logic in VLSI design$f[edited by] Jon T. Butler
210   $aLos Alamitos (CA)$cIEEE Computer Society Press$aNew York$cInstitute of Electrical and Electronics Engineer$d1991
215   $aVII, 120 p.$cill.$d28 cm
225 | $aIEEE computer society press technology series
312   $aTit. della cop.: Multiple-valued logic in VLSI$9NAP0501643
410  0$1001PUV0038070$12001 $aIEEE computer society press technology series
517 1 $aMultiple-valued logic in VLSI$9NAP0501643
606   $aCircuiti integrati$xProgettazione$2FIR$3NAPC221616$9I
606   $aCircuiti logici$2FIR$3NAPC024222$9I
676   $a621.39$9INGEGNERIA DEGLI ELABORATORI$v14
676   $a621.395$9INGEGNERIA DEGLI ELABORATORI. CIRCUITERIA$v22
702  1$aButler$b, Jon T.$3NAPV116574$4340
801  3$aIT$bIT-NA0079$c20110111
850   $aIT-BN0095          
912   $aNAP0501640
950  0$aBiblioteca Centralizzata di Ateneo$c1 v.$d 01SALA DING 621.39                  MULVLI$e 0102 0000008705    B A4                    1 v.$f3 $h19940413$i20110111
977   $a 01
996   $aMultiple-valued logic in VLSI design$91491931
997   $aUNISANNIO