LEADER 01313nam0 22003613i 450 
001 NAP0501585
005 20251003044254.0
010   $a0894644637
100   $a20110110d1990    ||||0itac50      ba
101 | $aeng
102   $aus
181  1$6z01$ai $bxxxe  
182  1$6z01$an
200 1 $aLogic design and switching theory$fSaburo Muroga
205   $aReprint with update
210   $aMalabar (FL)$cKrieger$d1990
215   $aXVI, 617 p.$d24 cm
606   $aCircuiti logici$2FIR$3CFIC015125$9E
606   $aCircuiti integrati$2FIR$3CFIC002586$9E
676   $a621.39$9INGEGNERIA DEGLI ELABORATORI$v14
676   $a621.395$9INGEGNERIA DEGLI ELABORATORI. CIRCUITERIA$v22
696   $aChip$aCircuiti elettronici integrati
699   $aCircuiti integrati$yChip
699   $aCircuiti integrati$yCircuiti elettronici integrati
700  1$aMuroga$b, Saburo$3UBOV006152$4070$049473
801  3$aIT$bIT-000000$c20110110
850   $aIT-BN0095          
901   $bNAP 01$cSALA DING $n$
912   $aNAP0501585
950  0$aBiblioteca Centralizzata di Ateneo$b1 v.$c1 v.$d 01SALA DING 621.39                  MUR.lo$e 0102 0000004205  VMA A4                    1 v.$fY $h19930915$i20110110
977   $a 01
996   $aLogic design and switching theory$91573535
997   $aUNISANNIO