LEADER 01318nam0 22003373i 450 
001 MIL0373798
005 20251003044232.0
010   $a0818677163
100   $a20101228d1997    ||||0itac50      ba
101 | $aeng
102   $aus
181  1$6z01$ai $bxxxe  
182  1$6z01$an
200 1 $aDigital design and modeling with VHDL and synthesis$fK. C. Chang
210   $aLos Alamitos [etc.]$cIEEE computer society press$d1997
215   $aXVI, 345 p.$d27 cm
606   $aCircuiti integrati$xProgettazione$2FIR$3MILC095947$9E
676   $a621.39$9INGEGNERIA DEGLI ELABORATORI$v14
676   $a621.395$9INGEGNERIA DEGLI ELABORATORI. CIRCUITERIA$v22
696   $aChip$aCircuiti elettronici integrati
699   $aCircuiti integrati$yChip
699   $aCircuiti integrati$yCircuiti elettronici integrati
700  1$aChang$b, Kou Chuan$f <1957-    >$3MILV201985$4070$0627331
801  3$aIT$bIT-000000$c20101228
850   $aIT-BN0095          
901   $bNAP 01$cSALA DING $n$
912   $aMIL0373798
950  0$aBiblioteca Centralizzata di Ateneo$b1 v.$c1 v.$d 01SALA DING 621.39                  CHA.di$e 0102 0000031695  VMA A4                    1 v.$fY $h19991216$i20101228
977   $a 01
996   $aDigital design and modeling with VHDL and synthesis$91213499
997   $aUNISANNIO