LEADER 07557nam 22007815 450 001 996465857503316 005 20200704231433.0 010 $a3-540-70670-4 024 7 $a10.1007/3-540-61730-2 035 $a(CKB)1000000000234521 035 $a(SSID)ssj0000323131 035 $a(PQKBManifestationID)11223081 035 $a(PQKBTitleCode)TC0000323131 035 $a(PQKBWorkID)10299227 035 $a(PQKB)11687950 035 $a(DE-He213)978-3-540-70670-0 035 $a(PPN)155189867 035 $a(EXLCZ)991000000000234521 100 $a20121227d1996 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aField-Programmable Logic, Smart Applications, New Paradigms and Compilers$b[electronic resource] $e6th International Workshop on Field-Programmable Logic and Applications, FPL '96, Darmstadt, Germany, September 23 - 25, Proceedings /$fedited by Reiner W. Hartenstein, Manfred Glesner 205 $a1st ed. 1996. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d1996. 215 $a1 online resource (X, 436 p.) 225 1 $aLecture Notes in Computer Science,$x0302-9743 ;$v1142 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-61730-2 327 $aPortable pipeline synthesis for FCCMs -- Performance-directed technology mapping for LUT-based FPGAs ? What role do decomposition and covering play? -- A framework for developing parametrised FPGA libraries -- FACT: Co-evaluation environment for FPGA architecture and CAD system -- An universal CLA adder generator for SRAM-based FPGAs -- An emulation system of the WASMII: A data driven computer on a virtual hardware -- Costum computing machines vs. Hardware/Software Co-Design: From a globalized point of view -- The design of a coprocessor board using Xilinx's XC6200 FPGA ? An experience report -- RACE: Reconfigurable and adaptive computing environment -- Computing 2-D DFTs using FPGAs -- CAPpartx: Computer aided prototyping partitioning for Xilinx FPGAs, a hierarchical partitioning tool for rapid prototyping -- Architectural synthesis and efficient circuit implementation for field programmable gate arrays -- RaPiD ? Reconfigurable pipelined datapath -- Solving satisfiability problems on FPGAs -- FPGA implementation of the block-matching algorithm for motion estimation in image coding -- Parallel CRC computation in FPGAs -- Coherent demodulation with FPGAs -- The Trianus system and its application to custom computing -- Logic synthesis for FPGAs using a mixed exclusive-/inclusive-OR form -- Flexible codesign target architecture for early prototyping of CMIST systems -- Attempt-1: A reconfigurable multiprocessor testbed -- A slow motion engine for the analysis of FPGA-based prototypes -- Implementing reconfigurable datapaths in FPGAs for adaptive filter design -- A fast constant coefficient multiplier for the XC6200 -- Key issues for user acceptance of FPGA design tools -- Reconfigurable DSP demonstrators for the development of spacecraft payload processors -- Reconfigurable logic based fibre channel network card with sub 2 ?s raw latency -- An asynchronous transfer mode (ATM) stream demultiplexer and switch -- Optically reconfigurable FPGAs: Is this a future trend? -- CCSimP ? An instruction-level costum-configurable processor for FPLDs -- Architectural synthesis techniques for dynamically reconfigurable logic -- Fast reconfigurable crossbar switching in FPGAs -- Growable FPGA macro generator -- Architectural strategies for implementing an image processing algorithm on XC6000 FPGA -- A virtual hardware operating system for the Xilinx XC6200 -- An experimental programmable environment for prototyping digital circuits -- Migration from schematic-based designs to a VHDL synthesis environment -- ASIC design and FPGA design: A unified design methodology applied to different technologies -- FIR filtering with FPGAs using quadrature sigma-delta modulation encoding -- A new FPGA technology mapping approach by cluster merging -- An EPLD based transient recorder for simulation of video signal processing devices in a VHDL environment close to system level conditions -- Convolutional error decoding with FPGAs -- Metastability characteristics testing for programmable logic design -- Implementing ?? modulator prototype designs on an FPGA -- Design of a VME parameterized library for FPGAs -- Development of a telephone answering machine in a lab ? FPGAs in Education -- FPGA design migration: Some remarks -- Concurrent design of hardware/software dedicated systems -- The implementation of a field programmable logic based co-processor for the acceleration of discrete event simulators -- Computing weight distributions of binary linear block codes on a CCM. 330 $aThis book constitutes the refereed proceedings of the 6th International Workshop of Field-Programmable Logic and Applications, FPL '96, held in Darmstadt, Germany, in September 1996. The 37 revised full papers presented in the book are selected from 82 submissions originating from 27 countries; also included are 13 high-quality poster presentations. The book is divided into topical sections on high-level design, new software and hardware development tools, custom computers, applications, hardware/software co-design, AISC emulators, vendor session, industrial applications and experiences, reconfiguration aspects, CAD user experiences, and miscellaneous. 410 0$aLecture Notes in Computer Science,$x0302-9743 ;$v1142 606 $aArchitecture, Computer 606 $aLogic design 606 $aMicroprocessors 606 $aComputational complexity 606 $aComputer-aided engineering 606 $aElectronics 606 $aMicroelectronics 606 $aComputer System Implementation$3https://scigraph.springernature.com/ontologies/product-market-codes/I13057 606 $aLogic Design$3https://scigraph.springernature.com/ontologies/product-market-codes/I12050 606 $aRegister-Transfer-Level Implementation$3https://scigraph.springernature.com/ontologies/product-market-codes/I12069 606 $aComplexity$3https://scigraph.springernature.com/ontologies/product-market-codes/T11022 606 $aComputer-Aided Engineering (CAD, CAE) and Design$3https://scigraph.springernature.com/ontologies/product-market-codes/I23044 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 615 0$aArchitecture, Computer. 615 0$aLogic design. 615 0$aMicroprocessors. 615 0$aComputational complexity. 615 0$aComputer-aided engineering. 615 0$aElectronics. 615 0$aMicroelectronics. 615 14$aComputer System Implementation. 615 24$aLogic Design. 615 24$aRegister-Transfer-Level Implementation. 615 24$aComplexity. 615 24$aComputer-Aided Engineering (CAD, CAE) and Design. 615 24$aElectronics and Microelectronics, Instrumentation. 676 $a621.39/5 702 $aHartenstein$b Reiner W$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aGlesner$b Manfred$4edt$4http://id.loc.gov/vocabulary/relators/edt 712 12$aInternational Workshop on Field-Programmable Logic and Applications 906 $aBOOK 912 $a996465857503316 996 $aField-Programmable Logic, Smart Applications, New Paradigms and Compilers$92829958 997 $aUNISA LEADER 00757nam a22002053a 4500 001 991003728519707536 008 080618s 000 0 eng d 020 $a0195505417 035 $ab13742802-39ule_inst 040 $aDip.to Lingue$bita 100 1 $aClark, Manning$0545838 245 10$aSources Of Australian History /$cManning Clark 260 $aMelbourne :$bOxford University Press,$c1977 300 $a622 p. ;$c19 cm 907 $a.b13742802$b28-01-14$c18-06-08 912 $a991003728519707536 945 $aLE012 Fondo Commonwealth 3-1-40$g1$i2012000301467$lle012$o-$pE0.00$q-$rn$so $t0$u0$v0$w0$x0$y.i14778488$z18-06-08 996 $aSources Of Australian History$91227432 997 $aUNISALENTO 998 $ale012$b18-06-08$cm$da $e-$feng$gat $h0$i0 LEADER 09083nam 22008055 450 001 996465886003316 005 20231220142112.0 010 $a3-540-40058-3 024 7 $a10.1007/11859802 035 $a(CKB)1000000000283701 035 $a(SSID)ssj0000315794 035 $a(PQKBManifestationID)11215202 035 $a(PQKBTitleCode)TC0000315794 035 $a(PQKBWorkID)10255231 035 $a(PQKB)10362367 035 $a(DE-He213)978-3-540-40058-5 035 $a(MiAaPQ)EBC3068033 035 $a(PPN)123138116 035 $a(EXLCZ)991000000000283701 100 $a20100301d2006 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aAdvances in Computer Systems Architecture$b[electronic resource] $e11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings /$fedited by Chris Jesshope, Colin Egan 205 $a1st ed. 2006. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2006. 215 $a1 online resource (XIV, 605 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4186 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-40056-7 320 $aIncludes bibliographical references and index. 327 $aThe Era of Multi-core Chips -A Fresh Look on Software Challenges -- Streaming Networks for Coordinating Data-Parallel Programs (Position Statement) -- Implementations of Square-Root and Exponential Functions for Large FPGAs -- Using Branch Prediction Information for Near-Optimal I-Cache Leakage -- Scientific Computing Applications on the Imagine Stream Processor -- Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination -- A Study of the Performance Potential for Dynamic Instruction Hints Selection -- Reorganizing UNIX for Reliability -- Critical-Task Anticipation Scheduling Algorithm for Heterogeneous and Grid Computing -- Processor Directed Dynamic Page Policy -- Static WCET Analysis Based Compiler-Directed DVS Energy Optimization in Real-Time Applications -- A Study on Transformation of Self-similar Processes with Arbitrary Marginal Distributions -- ?TC ? An Intermediate Language for Programming Chip Multiprocessors -- Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays -- Trace-Based Data Cache Leakage Reduction at Link Time -- Parallelizing User-Defined and Implicit Reductions Globally on Multiprocessors -- Overload Protection for Commodity Network Appliances -- An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit -- A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster -- Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor -- Combining Wireless Sensor Network with Grid for Intelligent City Traffic -- A Novel Processor Architecture for Real-Time Control -- A 0-1 Integer Linear Programming Based Approach for Global Locality Optimizations -- Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs -- Entropy Throttling: A Physical Approach for Maximizing Packet Mobility in Interconnection Networks -- Design of an Efficient Flexible Architecture for Color Image Enhancement -- Hypercube Communications on Optical Chordal Ring Networks with Chord Length of Three -- PMPS(3): A Performance Model of Parallel Systems -- Issues and Support for Dynamic Register Allocation -- A Heterogeneous Multi-core Processor Architecture for High Performance Computing -- Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation -- Fault-Free Pairwise Independent Hamiltonian Paths on Faulty Hypercubes -- Constructing Node-Disjoint Paths in Enhanced Pyramid Networks -- Striping Cache: A Global Cache for Striped Network File System -- DTuplesHPC: Distributed Tuple Space for Desktop High Performance Computing -- The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid Multiplier -- Live Range Aware Cache Architecture -- The Challenges of Efficient Code-Generation for Massively Parallel Architectures -- Reliable Systolic Computing Through Redundancy -- A Diversity-Controllable Genetic Algorithm for Optimal Fused Traffic Planning on Sensor Networks -- A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling -- On the Reliability of Drowsy Instruction Caches -- Design of a Reconfigurable Cryptographic Engine -- Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors -- The New BCD Subtractor and Its Reversible Logic Implementation -- Power-Efficient Microkernel of Embedded Operating System on Chip -- Understanding Prediction Limits Through Unbiased Branches -- Bandwidth Optimization of the EMCI for a High Performance 32-bit DSP -- Research on Petersen Graphs and Hyper-cubes Connected Interconnection Networks -- Cycle Period Analysis and Optimization of Timed Circuits -- Acceleration Techniques for Chip-Multiprocessor Simulator Debug -- A DDL?Based Software Architecture Model -- Branch Behavior Characterization for Multimedia Applications -- Optimization and Evaluating of StreamYGX2 on MASA Stream Processor -- SecureTorrent: A Security Framework for File Swarming -- Register Allocation on Stream Processor with Local Register File -- A Self-reconfigurable System-on-Chip Architecture for Satellite On-Board Computer Maintenance -- Compile-Time Thread Distinguishment Algorithm on VIM-Based Architecture -- Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining -- Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications -- Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols -- An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors -- An Efficient Approach to Energy Saving in Microcontrollers. 330 $aOn behalf of all of the people involved in the program selection, the program committee members as well as numerous other reviewers, we are both relieved and pleased to present you with the proceedings of the 2006 Asia-Pacific Computer Systems Architecture Conference (ACSAC 2006), which is being hosted in Shanghai on September 6?8, 2006. This is the 11th in a series of conferences, which started life in Australia, as the computer architecture component of the Australian Computer Science Week. In 1999 it ventured away from its roots for the first time, and the fourth Australasian Computer Architecture Conference was held in the beautiful city of Sails (Auckland, New Zealand). Perhaps it was because of a lack of any other computer architecture conference in Asia or just the attraction of traveling to the Southern Hemisphere but the conference became increasingly international during the subsequent three years and also changed its name to include Computer Systems Architecture, reflecting more the scope of the conference, which embraces both architectural and systems issues. In 2003, the conference again ventured offshore to reflect its constituency and since then has been held in Japan in the beautiful city of Aizu-Wakamatsu, followed by Beijing and Singapore. This year it again returns to China and next year will move to Korea for the first time, where it will be organized by the Korea University. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4186 606 $aComputer systems 606 $aComputer arithmetic and logic units 606 $aComputer input-output equipment 606 $aLogic design 606 $aComputer networks 606 $aMicroprocessors 606 $aComputer architecture 606 $aComputer System Implementation 606 $aArithmetic and Logic Structures 606 $aInput/Output and Data Communications 606 $aLogic Design 606 $aComputer Communication Networks 606 $aProcessor Architectures 615 0$aComputer systems. 615 0$aComputer arithmetic and logic units. 615 0$aComputer input-output equipment. 615 0$aLogic design. 615 0$aComputer networks. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 14$aComputer System Implementation. 615 24$aArithmetic and Logic Structures. 615 24$aInput/Output and Data Communications. 615 24$aLogic Design. 615 24$aComputer Communication Networks. 615 24$aProcessor Architectures. 676 $a004.2/2 702 $aJesshope$b Chris$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aEgan$b Colin$f1956-$4edt$4http://id.loc.gov/vocabulary/relators/edt 712 12$aACSAC (Asia-Pacific Computer Systems Architecture Conference) 906 $aBOOK 912 $a996465886003316 996 $aAdvances in Computer Systems Architecture$9772404 997 $aUNISA