LEADER 01299nam 2200397 450 001 000003394 005 20100225104800.0 100 $a--------d1929----km-y0itay0103----ba 101 0 $aeng 102 $aUS 200 1 $aUltima thule$fby Henry Handel Richardson 200 1 $a1 $n0004294 210 $aNew York$cNorton$dc1929 215 $a314 p.$d19 cm. 676 $a823$v(20. ed.)$9Narrativa inglese 700 1$aRichardson,$bHenry Handel$0439173 801 0$aIT$bUniversità della Basilicata - B.I.A.$gRICA$2unimarc 912 $a000003394 996 $aUltima thule$972388 997 $aUNIBAS BAS $aMONLET BAS $aMONOGR BAS $aLETTERE CAT $aLOTITO$b01$c19991015$lBAS01$h1330 CAT $aDILEO$b01$c19991019$lBAS01$h1229 CAT $c20000920$lBAS01$h1831 CAT $c20001010$lBAS01$h1634 CAT $c20050601$lBAS01$h1753 CAT $abatch$b01$c20050718$lBAS01$h1048 CAT $c20050718$lBAS01$h1107 CAT $c20050718$lBAS01$h1137 CAT $c20050718$lBAS01$h1151 CAT $aBATCH$b00$c20070503$lBAS01$h1733 CAT $aATR$b40$c20100225$lBAS01$h1048 FMT Z30 -1$lBAS01$LBAS01$mBOOK$1BASA1$APolo Storico-Umanistico$2GEN$BCollezione generale$3FP/4220$9FP/4220$64220$5L4220$819991015$f02$FPrestabile Generale LEADER 03640nam a2200325Ii 4500 001 991003238339707536 008 070806s2005 enka fsb 001 0 eng d 020 $a9780750660792 020 $a0750660791 035 $ab13653507-39ule_inst 040 $aBibl. Dip.le Aggr. Ingegneria Innovazione - Sez. Ingegneria Innovazione$beng 082 04$a621.366$222 100 1 $aIon, John C.$0498674 245 10$aLaser processing of engineering materials$h[e-book] :$bprinciples, procedure and industrial application /$cJohn C. Ion 260 $aOxford :$bBoston :$bElsevier/Butterworth-Heinemann,$c2005 300 $axviii, 556 p. :$bill. ;$c26 cm 504 $aIncludes bibliographical references and index 505 0 $aIntroduction; Evolution of Laser Material Processing; Lasers; Systems for Material Processing; Engineering Materials; Laser Processing Diagrams; Athermal Processing; Structural Change; Surface Hardening; Deformation and Fracture; Surface Melting; Cladding; Conduction Joining; Cutting; Marking; Keyhole Welding; Thermal Machining; Opportunities; Glossary; Appendices 520 $aThe complete guide to understanding and using lasers in material processing! Lasers are now an integral part of modern society, providing extraordinary opportunities for innovation in an ever-widening range of material processing and manufacturing applications. The study of laser material processing is a core element of many materials and manufacturing courses at undergraduate and postgraduate level. As a consequence, there is now a vast amount of research on the theory and application of lasers to be absorbed by students, industrial researchers, practising engineers and production managers. Written by an acknowledged expert in the field with over twenty years' experience in laser processing, John Ion distils cutting-edge information and research into a single key text. Essential for anyone studying or working with lasers, Laser Processing of Engineering Materials provides a clear explanation of the underlying principles, including physics, chemistry and materials science, along with a framework of available laser processes and their distinguishing features and variables. This book delivers the knowledge needed to understand and apply lasers to the processing of engineering materials, and is highly recommended as a valuable guide to this revolutionary manufacturing technology. * The first single volume text that treats this core engineering subject in a systematic manner * Covers the principles, practice and application of lasers in all contemporary industrial processes; packed with examples, materials data and analysis, and modelling techniques * Accompanied by extensive examination questions plus a companion website with instructor's solutions manual 533 $aElectronic reproduction.$bAmsterdam :$cElsevier Science & Technology,$d2007.$nMode of access: World Wide Web.$nSystem requirements: Web browser.$nTitle from title screen (viewed on Aug. 2, 2007).$nAccess may be restricted to users at subscribing institutions 650 0$aLasers$xIndustrial applications 650 6$aLasers$xApplications industrielles 655 7$aElectronic books.$2local 776 1 $cOriginal$z0750660791$z9780750660792$w(OCoLC)59719945 856 40$3Referex$uhttp://www.sciencedirect.com/science/book/9780750660792$zAn electronic book accessible through the World Wide Web; click for information 907 $a.b13653507$b07-04-22$c24-01-08 912 $a991003238339707536 996 $aLaser processing of engineering materials$9734305 997 $aUNISALENTO 998 $ale026$b24-01-08$cm$d@ $e-$feng$genk$h0$i0 LEADER 05930nam 2200853Ia 450 001 9910809174903321 005 20250318172315.0 010 $a9786613373892 010 $a9781119995739 010 $a1119995736 010 $a9780470977972 010 $a0470977973 010 $a9781283373890 010 $a1283373890 010 $a9780470977927 010 $a0470977922 010 $a9781119995852 010 $a111999585X 035 $a(CKB)3460000000003457 035 $a(EBL)675308 035 $a(SSID)ssj0000482438 035 $a(PQKBManifestationID)11296392 035 $a(PQKBTitleCode)TC0000482438 035 $a(PQKBWorkID)10526565 035 $a(PQKB)11102905 035 $a(Au-PeEL)EBL675308 035 $a(CaPaEBR)ebr10510475 035 $a(CaONFJC)MIL337389 035 $a(OCoLC)729726229 035 $a(CaSebORM)9780470688472 035 $a(MiAaPQ)EBC675308 035 $a(PPN)242964982 035 $a(OCoLC)810071451 035 $a(OCoLC)ocn810071451 035 $a(Perlego)1014735 035 $a(EXLCZ)993460000000003457 100 $a20101129d2011 uy 0 101 0 $aeng 135 $aurunu||||| 181 $ctxt 182 $cc 183 $acr 200 10$aVHDL for logic synthesis /$fAndrew Rushton 205 $a3rd ed. 210 $aChichester, West Sussex, U.K. $cWiley$d2011 215 $a1 online resource (486 p.) 300 $aDescription based upon print version of record. 311 08$a9780470688472 311 08$a0470688475 320 $aIncludes bibliographical references and index. 327 $aVHDL FOR LOGIC SYNTHESIS; Contents; Preface; List of Figures; List of Tables; 1 Introduction; 1.1 The VHDL Design Cycle; 1.2 The Origins of VHDL; 1.3 The Standardisation Process; 1.4 Unification of VHDL Standards; 1.5 Portability; 2 Register-Transfer Level Design; 2.1 The RTL Design Stages; 2.2 Example Circuit; 2.3 Identify the Data Operations; 2.4 Determine the Data Precision; 2.5 Choose Resources to Provide; 2.6 Allocate Operations to Resources; 2.7 Design the Controller; 2.8 Design the Reset Mechanism; 2.9 VHDL Description of the RTL Design; 2.10 Synthesis Results; 3 Combinational Logic 327 $a3.1 Design Units 3.2 Entities and Architectures; 3.3 Simulation Model; 3.4 Synthesis Templates; 3.5 Signals and Ports; 3.6 Initial Values; 3.7 Simple Signal Assignments; 3.8 Conditional Signal Assignments; 3.9 Selected Signal Assignment; 3.10 Worked Example; 4 Basic Types; 4.1 Synthesisable Types; 4.2 Standard Types; 4.3 Standard Operators; 4.4 Type Bit; 4.5 Type Boolean; 4.6 Integer Types; 4.7 Enumeration Types; 4.8 Multi-Valued Logic Types; 4.9 Records; 4.10 Arrays; 4.11 Aggregates, Strings and Bit-Strings; 4.12 Attributes; 4.13 More on Selected Signal Assignments; 5 Operators 327 $a5.1 The Standard Operators 5.2 Operator Precedence; 5.3 Boolean Operators; 5.4 Comparison Operators; 5.5 Shifting Operators; 5.6 Arithmetic Operators; 5.7 Concatenation Operator; 6 Synthesis Types; 6.1 Synthesis Type System; 6.2 Making the Packages Visible; 6.3 Logic Types - Std_Logic_1164; 6.4 Numeric Types - Numeric_Std; 6.5 Fixed-Point Types - Fixed_Pkg; 6.6 Floating-Point Types - Float_Pkg; 6.7 Type Conversions; 6.8 Constant Values; 6.9 Mixing Types in Expressions; 6.10 Top-Level Interface; 7 Std_Logic_Arith; 7.1 The Std_Logic_Arith Package; 7.2 Contents of Std_Logic_Arith 327 $a7.3 Type Conversions 7.4 Constant Values; 7.5 Mixing Types in Expressions; 8 Sequential VHDL; 8.1 Processes; 8.2 Signal Assignments; 8.3 Variables; 8.4 If Statements; 8.5 Case Statements; 8.6 Latch Inference; 8.7 Loops; 8.8 Worked Example; 9 Registers; 9.1 Basic D-Type Register; 9.2 Simulation Model; 9.3 Synthesis Model; 9.4 Register Templates; 9.5 Register Types; 9.6 Clock Types; 9.7 Clock Gating; 9.8 Data Gating; 9.9 Asynchronous Reset; 9.10 Synchronous Reset; 9.11 Registered Variables; 9.12 Initial Values; 10 Hierarchy; 10.1 The Role of Components; 10.2 Indirect Binding; 10.3 Direct Binding 327 $a10.4 Component Packages 10.5 Parameterised Components; 10.6 Generate Statements; 10.7 Worked Examples; 11 Subprograms; 11.1 The Role of Subprograms; 11.2 Functions; 11.3 Operators; 11.4 Type Conversions; 11.5 Procedures; 11.6 Declaring Subprograms; 11.7 Worked Example; 12 Special Structures; 12.1 Tristates; 12.2 Finite State Machines; 12.3 RAMs and Register Banks; 12.4 Decoders and ROMs; 13 Test Benches; 13.1 Test Benches; 13.2 Combinational Test Bench; 13.3 Verifying Responses; 13.4 Clocks and Resets; 13.5 Other Standard Types; 13.6 Don't Care Outputs; 13.7 Printing Response Values 327 $a13.8 Using TextIO to Read Data Files 330 $aMaking VHDL a simple and easy-to-use hardware description language Many engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This book bridges the gap between the VHDL language and the hardware that results from logic synthesis with clear organisation, progressing from the basics of combinational logic, types, and operators; through special structures such as tristate buses, register banks and memories, to advanced themes such as developing your own packages, writing test benches and using the 517 3 $aVHSIC Hardware Description Language for logic synthesis 606 $aVHDL (Computer hardware description language) 606 $aLogic design$xData processing 606 $aComputer-aided design 615 0$aVHDL (Computer hardware description language) 615 0$aLogic design$xData processing. 615 0$aComputer-aided design. 676 $a621.39/5 686 $aCOM059000$2bisacsh 700 $aRushton$b Andrew$0771816 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910809174903321 996 $aVHDL for logic synthesis$94006985 997 $aUNINA