LEADER 01348nam a2200301 i 4500 001 991002843219707536 005 20040406075752.0 008 040624s1991 it a 001 0 ita 020 $a8870627136 035 $ab12986471-39ule_inst 035 $aARCHE-094415$9ExL 040 $aDip.to Beni Culturali$bita$cA.t.i. Arché s.c.r.l. Pandora Sicilia s.r.l. 082 04$a937.07 100 1 $aBraccesi, Lorenzo$038657 245 10$aAlessandro e la Germania :$briflessioni sulla geografia romana di conquista /$cLorenzo Braccesi 260 $aRoma :$bL'Erma di Bretschneider,$c1991 300 $a143 p., [6] p. di tav. :$bill. ;$c23 cm 440 0$aProblemi e ricerche di storia antica ;$v13 600 04$aAlessandro :$cMagno 651 4$aRoma antica$xConquiste 907 $a.b12986471$b02-04-14$c12-07-04 912 $a991002843219707536 945 $aLE001 SR I 60$g1$i2001000033034$lle001$nC. 1$o-$pE0.00$q-$rl$s- $t0$u0$v0$w0$x0$y.i13591071$z12-07-04 945 $aLE016 GRE 6 367 $g1$i2016000059250$lle016$nFondo Nenci$on$pE10.00$q-$rn$so $t0$u0$v0$w0$x0$y.i14397882$z15-03-07 945 $aLE027 R-XV/A 43$g1$i2027000121779$lle027$o-$pE35.00$q-$rl$s- $t0$u0$v0$w0$x0$y.i14243763$z31-05-06 996 $aAlessandro e la Germania$9284207 997 $aUNISALENTO 998 $ale001$ale016$ale027$b12-07-04$cm$da $e-$fita$git $h0$i3 LEADER 03957nam 2200493 450 001 996499854203316 005 20231110220840.0 010 $a3-031-16027-4 035 $a(MiAaPQ)EBC7146410 035 $a(Au-PeEL)EBL7146410 035 $a(CKB)25461615500041 035 $a(PPN)266349730 035 $a(EXLCZ)9925461615500041 100 $a20230408d2023 uy 0 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 00$aLogic synthesis for VLSI-based combined finite state machines $esynthesis targeting ASICs, CPLDs and FPGAs /$fedited by Alexander Barkalov [and four others] 210 1$aCham, Switzerland :$cSpringer,$d[2023] 210 4$d©2023 215 $a1 online resource (305 pages) 225 1 $aLecture Notes in Electrical Engineering ;$vv.922 311 08$aPrint version: Barkalov, Alexander Logic Synthesis for VLSI-Based Combined Finite State Machines Cham : Springer International Publishing AG,c2023 9783031160264 320 $aIncludes bibliographical references and index. 327 $aIntro -- Preface -- Contents -- Abbreviations -- 1 Control Algorithms and Finite State Machines -- 1.1 Methods of Implementation of Control Algorithms -- 1.2 Basic Models of Finite State Machines -- 1.3 Synthesis of Mealy FSM -- 1.4 Synthesis of Moore FSM -- 1.5 Synthesis of Microprogram Control Units -- 1.6 Background of Combined FSMs -- References -- 2 VLSI-based Logic Synthesis -- 2.1 Evaluation of Logic Elements -- 2.2 Logic Synthesis with ASICs -- 2.3 Logic Synthesis with CPLDs -- 2.4 Logic Synthesis with FPGAs -- References -- 3 ASIC-based Synthesis of CFSMs -- 3.1 Trivial Matrix Implementation -- 3.2 Structural Decomposition for Matrix CFSMs -- 3.3 PES-based Matrix Circuits of Moore FSMs -- 3.4 Analysis of CFSM-based Matrix Circuits -- References -- 4 Optimization of ASIC-based CFSMs -- 4.1 CFSMs with Optimal State Assignment -- 4.2 CFSMs with Transformation of State Codes -- 4.3 CFSMs with Partial Code Transformation -- 4.4 CFSMs with Primary Encoding of Classes of PES -- References -- 5 Homogenous CPLD-Based Synthesis of CFSMs -- 5.1 Preliminary Information -- 5.2 Synthesis of P CFSM -- 5.3 Synthesis of CFSMs with Optimal State Assignment -- 5.4 Synthesis of CFSMs with Transformation of State Codes -- 5.5 Synthesis of CFSMs with Primary Encoding of Classes -- References -- 6 Heterogeneous CPLD-based Synthesis of CFSMs -- 6.1 Preliminary Information -- 6.2 Synthesis of CFSMs with Trivial State Assignment -- 6.3 Synthesis of CFSMs with Optimal State Assignment -- 6.4 Synthesis of CFSMs with Primary Encoding of Classes -- 6.5 Synthesis of CFSMs with Transformation of Object Codes -- References -- 7 CPLD-Based Synthesis with Transformation of State Codes -- 7.1 Synthesis with Complete State Transformation -- 7.2 Partial State Transformation: Homogenous CPLDs -- 7.3 Partial State Transformation: Heterogenous CPLDs. 327 $a7.4 Combining Different Methods of Object Transformation -- References -- 8 FPGA-Based Synthesis of CFSMs -- 8.1 Preliminary Information -- 8.2 Primary Encoding of Classes of PES for FPGA-Based GFSMs -- 8.3 FPGA-Based Synthesis with Transformation of Class Codes -- 8.4 Twofold State Assignment in CFSMs -- References -- Appendix Conclusion -- Index. 410 0$aLecture Notes in Electrical Engineering 606 $aIntegrated circuits$xVery large scale integration 606 $aAutomatic control 606 $aSequential machine theory 615 0$aIntegrated circuits$xVery large scale integration. 615 0$aAutomatic control. 615 0$aSequential machine theory. 676 $a629.8 702 $aBarkalov$b Alexander 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a996499854203316 996 $aLogic synthesis for VLSI-based combined finite state machines$93084146 997 $aUNISA