LEADER 00948cam a2200241/i 4500 001 991001610009707536 008 120224s 000 0 fre d 020 $a2600004564 035 $ab14041613-39ule_inst 040 $aDip.to Filologia Ling. e Lett.$bita 130 0 $aVie de saint Alexis$91442070 245 13$aLa vie de Saint Alexis /$cédition critique par Maurizio Perugi 260 $aGenève :$bDroz,$c2000 300 $a319 p. ;$c18 cm. 440 0$aTextes littéraires francais ;$v529 500 $aBibliografia: p. 265-280 700 1 $aPerugi, Maurizio $eauthor$4http://id.loc.gov/vocabulary/relators/aut$0155026 907 $a.b14041613$b02-04-14$c24-02-12 912 $a991001610009707536 945 $aLE008 FL.M. (f.r.) XIV 428$g1$i2008000018917$lle008$o-$pE0.00$q-$rl$s- $t0$u0$v0$w0$x0$y.i15385036$z24-02-12 996 $aVie de saint Alexis$91442070 997 $aUNISALENTO 998 $ale008$b24-02-12$cm$da $e-$ffre$gsz $h3$i0 LEADER 03380nam 22006975 450 001 9910280950703321 005 20251225210914.0 010 $a3-319-90023-4 024 7 $a10.1007/978-3-319-90023-0 035 $a(CKB)4530000000000071 035 $a(DE-He213)978-3-319-90023-0 035 $a(MiAaPQ)EBC6285654 035 $a(MiAaPQ)EBC5579030 035 $a(Au-PeEL)EBL5579030 035 $a(OCoLC)1066178693 035 $a(PPN)226695972 035 $a(EXLCZ)994530000000000071 100 $a20180416d2017 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aSystem Level Design from HW/SW to Memory for Embedded Systems $e5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguaçu, Brazil, November 3?6, 2015, Proceedings /$fedited by Marcelo Götz, Gunar Schirner, Marco Aurélio Wehrmeister, Mohammad Abdullah Al Faruque, Achim Rettberg 205 $a1st ed. 2017. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2017. 215 $a1 online resource (XII, 231 p. 92 illus.) 225 1 $aIFIP Advances in Information and Communication Technology,$x1868-422X ;$v523 300 $aIncludes index. 311 08$a3-319-90022-6 330 $aThis book constitutes the refereed proceedings of the 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, held in Foz do Iguaçu, Brazil, in November 2015. The 18 full revised papers presented were carefully reviewed and selected from 25 submissions. The papers present a broad discussion on the design, analysis and verification of embedded and cyber-physical systems including design methodologies, verification, performance analysis, and real-time systems design. They are organized in the following topical sections: cyber-physical systems, system-level design; multi/many-core system design; memory system design; and embedded HW/SW design and applications. 410 0$aIFIP Advances in Information and Communication Technology,$x1868-422X ;$v523 606 $aComputers, Special purpose 606 $aComputers 606 $aComputer systems 606 $aSoftware engineering 606 $aSpecial Purpose and Application-Based Systems 606 $aComputer Hardware 606 $aComputer System Implementation 606 $aSoftware Engineering 615 0$aComputers, Special purpose. 615 0$aComputers. 615 0$aComputer systems. 615 0$aSoftware engineering. 615 14$aSpecial Purpose and Application-Based Systems. 615 24$aComputer Hardware. 615 24$aComputer System Implementation. 615 24$aSoftware Engineering. 676 $a004.16 702 $aGötz$b Marcelo$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aSchirner$b Gunar$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aWehrmeister$b Marco Aurélio$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aAl Faruque$b Mohammad Abdullah$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aRettberg$b Achim$4edt$4http://id.loc.gov/vocabulary/relators/edt 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910280950703321 996 $aSystem Level Design from HW$92527900 997 $aUNINA