LEADER 01696nam a2200337 i 4500 001 991001234559707536 005 20020507113227.0 008 970308s1963 us ||| | eng 035 $ab1019230x-39ule_inst 035 $aLE00644377$9ExL 040 $aDip.to Fisica$bita 084 $a53(082.2) 084 $a53.3.1 084 $a539.72 111 2 $aCourse of the International School of Physics "Enrico Fermi" on selected topics on elementary particle physics$0463850 245 10$aSelected topics on elementary particle physics = Argomenti scelti sulla fisica delle particelle elementari :$bproceedings of the International School of Physics "Enrico Fermi", Course XXVI (Varenna on Lake Como, Villa Monastero, July 23-August 4 1962) /$cedited by M. Conversi ; Italian Physical Society 260 $aNew York :$bAcademic Press, Inc.,$c1963 300 $aviii, 294 p. ;$c24 cm. 490 0 $aProceedings of the International School of Physics "Enrico Fermi" ;$v26 490 0 $aRendiconti della Scuola Internazionale di Fisica "Enrico Fermi" ;$v26 650 4$aElementary particles$xCongresses 700 1 $aConversi, M. 710 2 $aInternational School of Physics "Enrico Fermi" 710 2 $aSIF 740 0 $aArgomenti scelti sulla fisica delle particelle elementari 907 $a.b1019230x$b17-02-17$c27-06-02 912 $a991001234559707536 945 $aLE006 53(042+082.2) VAR$g1$i2006000035873$lle006$o-$pE0.00$q-$rl$s- $t0$u0$v0$w0$x0$y.i1023729x$z27-06-02 996 $aSelected topics on elementary particle physics = Argomenti scelti sulla fisica delle particelle elementari$9191577 997 $aUNISALENTO 998 $ale006$b01-01-97$cm$da $e-$feng$gus $h0$i1 LEADER 07166nam 2200589 450 001 996466147803316 005 20230515153442.0 010 $a3-540-68066-7 024 7 $a10.1007/BFb0055226 035 $a(CKB)1000000000210982 035 $a(SSID)ssj0000323127 035 $a(PQKBManifestationID)11242974 035 $a(PQKBTitleCode)TC0000323127 035 $a(PQKBWorkID)10288685 035 $a(PQKB)10167483 035 $a(DE-He213)978-3-540-68066-6 035 $a(MiAaPQ)EBC7202801 035 $a(Au-PeEL)EBL7202801 035 $a(PPN)155180320 035 $a(EXLCZ)991000000000210982 100 $a20230515d1998 uy 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 00$aField-programmable logic and applications $efrom FPGAs to computing paradigm : 8th international workshop, FPL'98 : Tallinn, Estonia, August 31-September 3, 1998 : proceedings /$fReiner W. Hartenstein and Andres Keevallik (editors) 205 $a1st ed. 1998. 210 1$aBerlin, Germany :$cSpringer,$d[1998] 210 4$dİ1998 215 $a1 online resource (XIII, 539 p.) 225 1 $aLecture Notes in Computer Science Series ;$vVolume 1482 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-64948-4 327 $aNew CAD framework extends simulation of dynamically reconfigurable logic -- Pebble: A language for parametrised and reconfigurable hardware design -- Integrated development environment for logic synthesis based on dynamically reconfigurable FPGAs -- Designing for Xilinx XC6200 FPGAs -- Perspectives of reconfigurable computing in research, industry and education -- Field-programmable logic: Catalyst for new computing paradigms -- Run-time management of dynamically reconfigurable designs -- Acceleration of satisfiability algorithms by reconfigurable hardware -- An optimized design flow for fast FPGA-based rapid prototyping -- A knowledge-based system for prototyping on FPGAs -- JVX ? A rapid prototyping system based on Java and FPGAs -- Prototyping new ILP architectures using FPGAs -- CAD system for ASM and FSM synthesis -- Fast floorplanning for FPGAs -- SRAM-based FPGAs: A fault model for the configurable logic modules -- Reconfigurable hardware as shared resource in multipurpose computers -- Reconfigurable computer array: The bridge between high speed sensors and low speed computing -- A reconfigurable engine for real-time video processing -- An FPGA implementation of a magnetic bearing controller for mechatronic applications -- Exploiting contemporary memory techniques in reconfigurable accelerators -- Self modifying circuitry ? A platform for tractable virtual circuitry -- REACT: Reactive environment for runtime reconfiguration -- Evaluation of the XC6200-series architecture for cryptographic applications -- An FPGA-based object recognition machine -- PCI-SCI protocol translations: Applying microprogramming concepts to FPGAs -- Instruction-level parallelism for reconfigurable computing -- A hardware/software co-design environment for reconfigurable logic systems -- Mapping loops onto reconfigurable architectures -- Speed optimization of the ALR circuit using an FPGA with embedded RAM: A design experience -- High-level synthesis for dynamically reconfigurable hardware/software systems -- Dynamic specialisation of XC6200 FPGAs by partial evaluation -- WebScope: A circuit debug tool -- Computing Goldbach partitions using pseudo-random bit generator operators on an FPGA systolic array -- Solving boolean satisfiability with dynamic hardware configurations -- Modular exponent realization on FPGAs -- Cost effective 2×2 inner product processors -- A field-programmable gate-array system for evolutionary computation -- A transmutable telecom system -- A survey of reconfigurable computing architectures -- A novel field programmable gate array architecture for high speed arithmetic processing -- Accelerating DTP with reconfigurable computing engines -- Hardware mapping of a parallel algorithm for matrix-vector multiplication overlapping communications and computations -- An interactive datasheet for the xilinx XC6200 -- Fast adaptive image processing in FPGAs using stack filters -- Increasing microprocessor performance with tightly-coupled reconfigurable logic arrays -- A high-performance computing module for a low earth orbit satellite using reconfigurable logic -- Maestro-link: A high performance interconnect for PC cluster -- A hardware implementation of Constraint Satisfaction Problem based on new reconfigurante LSI architecture -- A hardware operating system for dynamic reconfiguration of FPGAs -- High speed low level image processing on FPGAs using distributed arithmetic -- A flexible implementation of high-performance FIR filters on Xilinx FPGAs -- Implementing processor arrays on FPGAs -- Reconfigurable hardware ? A study in codesign -- Statechart-based HW/SW-codesign of a multi-FPGA-board and a microprocessor -- Simulation of ATM switches using dynamically reconfigurable FPGA's -- Fast prototyping using system emulators -- Space-efficient mapping of 2D-DCT onto dynamically configurable coarse-grained architectures -- XILINX4000 architecture ? Driven synthesis for speed -- The PLD-implementation of Boolean function characterized by minimum delay -- Reconfigurable PCI-BUS interface (RPCI) -- Programmable prototyping system for image processing -- A co-simulation concept for an efficient analysis of complex logic designs -- Programming and implementation of reconfigurable routers -- Virtual instruments based on reconfigurable logic -- The >S