LEADER 00457oas 2200157z- 450 001 9910139409503321 035 $a(CKB)2480000000008503 035 $a(EXLCZ)992480000000008503 100 $a20170515cuuuuuuuu -u- - 101 0 $aeng 200 00$aJournal of Bioinformatics and Sequence Analysis 210 $cAcademic Journals 906 $aJOURNAL 912 $a9910139409503321 996 $aJournal of bioinformatics and sequence analysis$91962324 997 $aUNINA LEADER 01482nam 2200349 450 001 996575406003316 005 20231209100043.0 010 $a0-7381-4777-X 024 7 $a10.1109/IEEESTD.2002.8894283 035 $a(CKB)4100000009825465 035 $a(NjHacI)994100000009825465 035 $a(EXLCZ)994100000009825465 100 $a20231209d2002 uy 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$a62142-2005 - IEC/IEEE iInternational standard - Verilog(R) Register Transfer Level synthesis /$fInstitute of Electrical and Electronics Engineers 210 1$aNew York, New York :$cIEEE,$d2002. 215 $a1 online resource (116 pages) 330 $aReplaces IEEE Std 1364.1-2002. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364. 517 $a62142-2005 - IEC/IEEE International Standard - Verilog 606 $aVHDL (Computer hardware description language) 615 0$aVHDL (Computer hardware description language) 676 $a621.392 801 0$bNjHacI 801 1$bNjHacl 906 $aDOCUMENT 912 $a996575406003316 996 $a62142-2005 - IEC$92581352 997 $aUNISA