LEADER 01501nam 2200385 450 001 996574994103316 005 20231214123449.0 010 $a1-5044-8866-0 024 70$a10.1109/IEEESTD.2022.9916221 035 $a(CKB)4100000012897136 035 $a(NjHacI)994100000012897136 035 $a(EXLCZ)994100000012897136 100 $a20231214d2022 uy 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$a1500-2022 - IEEE Standard Testability Method for Embedded Core-based Integrated Circuits /$fIEEE 210 1$aNew York :$cIEEE,$d2022. 215 $a1 online resource (168 pages) 330 $aA mechanism for the test of core designs within a system on chip (SoC) is defined. This mechanism is a hardware architecture and the core test language (CTL) is leveraged to facilitate communication between core designers and core integrators. 606 $aIntegrated circuits$xTesting 606 $aEmbedded computer systems$xTesting 606 $aSystems on a chip$xTesting$xStandards 615 0$aIntegrated circuits$xTesting. 615 0$aEmbedded computer systems$xTesting. 615 0$aSystems on a chip$xTesting$xStandards. 676 $a621.3815 801 0$bNjHacI 801 1$bNjHacl 906 $aDOCUMENT 912 $a996574994103316 996 $a1500-2022 - IEEE Standard Testability Method for Embedded Core-based Integrated Circuits$93882316 997 $aUNISA