LEADER 02662nam 2200385 450 001 996574986503316 005 20231214123445.0 010 $a1-5044-8875-X 024 70$a10.1109/IEEESTD.2022.9919140 035 $a(CKB)4100000012897135 035 $a(NjHacI)994100000012897135 035 $a(EXLCZ)994100000012897135 100 $a20231214d2022 uy 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$a1149.7-2022 - IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture /$fIEEE 210 1$aNew York :$cIEEE,$d2022. 215 $a1 online resource (1048 pages) 330 $aCircuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1 is described in this standard. The circuitry uses IEEE Std 1149.1 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of IEEE 1149.7 Test Access Ports (TAP.7s), T0 to T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a four-wire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes IEEE 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrently with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability. 606 $aElectronic controllers 606 $aDebugging in computer science 606 $aBoundary scan testing 615 0$aElectronic controllers. 615 0$aDebugging in computer science. 615 0$aBoundary scan testing. 676 $a621.46 801 0$bNjHacI 801 1$bNjHacl 906 $aDOCUMENT 912 $a996574986503316 996 $a1149.7-2022 - IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture$93882245 997 $aUNISA