LEADER 01148nam 2200337 450 001 996574671203316 005 20231214024958.0 010 $a1-5044-7426-0 035 $a(CKB)4100000011774093 035 $a(NjHacI)994100000011774093 035 $a(EXLCZ)994100000011774093 100 $a20231214d2009 uy 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$a1800-2009 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language - Redline /$fInstitute of Electrical and Electronics Engineers 210 1$a[Place of publication not identified] :$cIEEE,$d2009. 215 $a1 online resource 606 $aFinish hardware 606 $aHardware industry 615 0$aFinish hardware. 615 0$aHardware industry. 676 $a683 801 0$bNjHacI 801 1$bNjHacl 906 $aDOCUMENT 912 $a996574671203316 996 $a1800-2009 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language - Redline$92581488 997 $aUNISA