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200 10$a62530-2-2023 - IEEE/IEC International Standard--SystemVerilog$iPart 2 $eUniversal Verification Methodology Language Reference Manual /$fIEEE
210  1$aNew York, USA :$cIEEE,$d2023.
215   $a1 online resource (461 pages)
330   $aThe Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.
606   $aVerification (Logic)
615  0$aVerification (Logic)
676   $a160
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