LEADER 01414nam  2200325   450 
001 996559964703316
005 20231205191952.0
010   $a979-88-557-0206-4
035   $a(CKB)28534579300041
035   $a(NjHacI)9928534579300041
035   $a(EXLCZ)9928534579300041
100   $a20231205d2023      uy             0
101 0 $aeng
135   $aur|||||||||||
181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 10$a61523-1-2023 - IEEE/IEC International Standard--Delay and power calculation standards$hPart 1 $eIntegrated Circuit (IC) Open Library Architecture (OLA) /$fIEEE
210  1$aNew York, USA :$cIEEE,$d2023.
215   $a1 online resource (646 pages)
330   $aWays for integrated circuit designers to analyze chip timing and power consistently across a broad set of electrical design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, the means by which EDA vendors can meet their application performance and capacity needs are discussed.
606   $aIntegrated circuit layout
615  0$aIntegrated circuit layout.
676   $a621.3
801  0$bNjHacI
801  1$bNjHacl
906   $aBOOK
912   $a996559964703316
996   $a61523-1-2023 - IEEE$93590376
997   $aUNISA