LEADER 05845nam 22008175 450 001 996466362503316 005 20230406051902.0 010 $a3-540-92990-8 024 7 $a10.1007/978-3-540-92990-1 035 $a(CKB)1000000000545823 035 $a(SSID)ssj0000318108 035 $a(PQKBManifestationID)11923574 035 $a(PQKBTitleCode)TC0000318108 035 $a(PQKBWorkID)10307409 035 $a(PQKB)11207503 035 $a(DE-He213)978-3-540-92990-1 035 $a(MiAaPQ)EBC3063842 035 $a(PPN)132868989 035 $a(EXLCZ)991000000000545823 100 $a20100301d2009 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aHigh Performance Embedded Architectures and Compilers$b[electronic resource] $eFourth International Conference, HiPEAC 2009 /$fedited by André Seznec, Joel Emer, Michael O'Boyle, Margaret Martonosi, Theo Ungerer 205 $a1st ed. 2009. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2009. 215 $a1 online resource (XIII, 420 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v5409 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-92989-4 327 $aInvited Program -- Keynote: Challenges on the Road to Exascale Computing -- Keynote: Compilers in the Manycore Era -- I Dynamic Translation and Optimisation -- Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering -- Predictive Runtime Code Scheduling for Heterogeneous Architectures -- Collective Optimization -- High Speed CPU Simulation Using LTU Dynamic Binary Translation -- II Low Level Scheduling -- Integrated Modulo Scheduling for Clustered VLIW Architectures -- Software Pipelining in Nested Loops with Prolog-Epilog Merging -- A Flexible Code Compression Scheme Using Partitioned Look-Up Tables -- III Parallelism and Resource Control -- MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor -- IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor -- A Hardware Task Scheduler for Embedded Video Processing -- Finding Stress Patterns in Microprocessor Workloads -- IV Communication -- Deriving Efficient Data Movement from Decoupled Access/Execute Specifications -- MPSoC Design Using Application-Specific Architecturally Visible Communication -- Communication Based Proactive Link Power Management -- V Mapping for CMPs -- Mapping and Synchronizing Streaming Applications on Cell Processors -- Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors -- Accomodating Diversity in CMPs with Heterogeneous Frequencies -- A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip -- VI Power -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines -- HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic -- Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures -- VII Cache Issues -- Revisiting Cache Block Superloading -- ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors -- In-Network Caching for Chip Multiprocessors -- VIII Parallel Embedded Applications -- Parallel LDPC Decoding on the Cell/B.E. Processor -- Parallel H.264 Decoding on an Embedded Multicore Processor. 330 $aThis book constitutes the refereed proceedings of the Fourth International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The 27 revised full papers presented together with 2 invited keynote paper were carefully reviewed and selected from 97 submissions. The papers are organized in topical sections on dynamic translation and optimisation, low level scheduling, parallelism and resource control, communication, mapping for CMPs, power, cache issues as well as parallel embedded applications. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v5409 606 $aComputer systems 606 $aComputer arithmetic and logic units 606 $aMicroprocessors 606 $aComputer architecture 606 $aComputer input-output equipment 606 $aLogic design 606 $aComputer networks 606 $aComputer System Implementation 606 $aArithmetic and Logic Structures 606 $aProcessor Architectures 606 $aInput/Output and Data Communications 606 $aLogic Design 606 $aComputer Communication Networks 615 0$aComputer systems. 615 0$aComputer arithmetic and logic units. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 0$aComputer input-output equipment. 615 0$aLogic design. 615 0$aComputer networks. 615 14$aComputer System Implementation. 615 24$aArithmetic and Logic Structures. 615 24$aProcessor Architectures. 615 24$aInput/Output and Data Communications. 615 24$aLogic Design. 615 24$aComputer Communication Networks. 676 $a003.3 702 $aSeznec$b André$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aEmer$b Joel$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aO'Boyle$b Michael$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aMartonosi$b Margaret$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aUngerer$b Theo$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a996466362503316 996 $aHigh Performance Embedded Architectures and Compilers$9772079 997 $aUNISA