LEADER 05982nam 22008055 450 001 996466358403316 005 20200630233916.0 010 $a3-540-28641-1 024 7 $a10.1007/b104218 035 $a(CKB)1000000000212658 035 $a(SSID)ssj0000225494 035 $a(PQKBManifestationID)11187086 035 $a(PQKBTitleCode)TC0000225494 035 $a(PQKBWorkID)10230442 035 $a(PQKB)10380666 035 $a(DE-He213)978-3-540-28641-7 035 $a(MiAaPQ)EBC3068375 035 $z(PPN)199770670 035 $a(PPN)134123530 035 $a(EXLCZ)991000000000212658 100 $a20100715d2005 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aPower-Aware Computer Systems$b[electronic resource] $eThird International Workshop, PACS 2003, San Diego, CA, USA, December 1, 2003, Revised Papers /$fedited by Babak Falsafi, T. N. Vijaykumar 205 $a1st ed. 2005. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2005. 215 $a1 online resource (X, 215 p.) 225 1 $aLecture Notes in Computer Science,$x0302-9743 ;$v3164 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-24031-4 320 $aIncludes bibliographical references and index. 327 $aCompilers -- Runtime Biased Pointer Reuse Analysis and Its Application to Energy Efficiency -- Inter-program Compilation for Disk Energy Reduction -- Embedded Systems -- Energy Consumption in Mobile Devices: Why Future Systems Need Requirements?Aware Energy Scale-Down -- Efficient Scratchpad Allocation Algorithms for Energy Constrained Embedded Systems -- Online Prediction of Battery Lifetime for Embedded and Mobile Devices -- Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture -- Heterogeneous Wireless Network Management -- Microarchitectural Techniques -- ?Look It Up? or ?Do the Math?: An Energy, Area, and Timing Analysis of Instruction Reuse and Memoization -- CPU Packing for Multiprocessor Power Reduction -- Exploring the Potential of Architecture-Level Power Optimizations -- Coupled Power and Thermal Simulation with Active Cooling -- Cache and Memory Systems -- The Synergy Between Power-Aware Memory Systems and Processor Voltage Scaling -- Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches -- PARROT: Power Awareness Through Selective Dynamically Optimized Traces. 330 $aWelcome to the proceedings of the 3rd Power-Aware Computer Systems (PACS 2003) Workshop held in conjunction with the 36th Annual International Symposium on Microarchitecture (MICRO-36). The increase in power and - ergy dissipation in computer systems has begun to limit performance and has also resulted in higher cost and lower reliability. The increase also implies - ducedbatterylifeinportablesystems.Becauseofthemagnitudeoftheproblem, alllevelsofcomputersystems,includingcircuits,architectures,andsoftware,are being employed to address power and energy issues. PACS 2003 was the third workshop in its series to explore power- and energy-awareness at all levels of computer systems and brought together experts from academia and industry. These proceedings include 14 research papers, selected from 43 submissions, spanningawidespectrumofareasinpower-awaresystems.Wehavegrouped the papers into the following categories: (1) compilers, (2) embedded systems, (3) microarchitectures, and (4) cache and memory systems. The ?rst paper on compiler techniques proposes pointer reuse analysis that is biased by runtime information (i.e., the targets of pointers are determined based on the likelihood of their occurrence at runtime) to map accesses to ener- e?cient memory access paths (e.g., avoid tag match). Another paper proposes compiling multiple programs together so that disk accesses across the programs can be synchronized to achieve longer sleep times in disks than if the programs are optimized separately. 410 0$aLecture Notes in Computer Science,$x0302-9743 ;$v3164 606 $aElectronics 606 $aMicroelectronics 606 $aArchitecture, Computer 606 $aComputer organization 606 $aComputer hardware 606 $aOperating systems (Computers) 606 $aElectrical engineering 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 606 $aComputer System Implementation$3https://scigraph.springernature.com/ontologies/product-market-codes/I13057 606 $aComputer Systems Organization and Communication Networks$3https://scigraph.springernature.com/ontologies/product-market-codes/I13006 606 $aComputer Hardware$3https://scigraph.springernature.com/ontologies/product-market-codes/I1200X 606 $aOperating Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/I14045 606 $aElectrical Engineering$3https://scigraph.springernature.com/ontologies/product-market-codes/T24000 615 0$aElectronics. 615 0$aMicroelectronics. 615 0$aArchitecture, Computer. 615 0$aComputer organization. 615 0$aComputer hardware. 615 0$aOperating systems (Computers). 615 0$aElectrical engineering. 615 14$aElectronics and Microelectronics, Instrumentation. 615 24$aComputer System Implementation. 615 24$aComputer Systems Organization and Communication Networks. 615 24$aComputer Hardware. 615 24$aOperating Systems. 615 24$aElectrical Engineering. 676 $a621.3916 702 $aFalsafi$b Babak$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aVijaykumar$b T. N$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a996466358403316 996 $aPower-Aware Computer Systems$9772835 997 $aUNISA