LEADER 05942nam 22007335 450 001 996466265803316 005 20200706215653.0 010 $a3-540-48469-8 024 7 $a10.1007/3-540-58179-0 035 $a(CKB)1000000000234130 035 $a(SSID)ssj0000322079 035 $a(PQKBManifestationID)11227107 035 $a(PQKBTitleCode)TC0000322079 035 $a(PQKBWorkID)10281457 035 $a(PQKB)10307470 035 $a(DE-He213)978-3-540-48469-1 035 $a(PPN)15519139X 035 $a(EXLCZ)991000000000234130 100 $a20121227d1994 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aComputer Aided Verification$b[electronic resource] $e6th International Conference, CAV '94, Stanford, California, USA, June 21-23, 1994. Proceedings /$fedited by David L. Dill 205 $a1st ed. 1994. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d1994. 215 $a1 online resource (X, 486 p.) 225 1 $aLecture Notes in Computer Science,$x0302-9743 ;$v818 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-58179-0 327 $aA determinizable class of timed automata -- Real-time system verification using P/T nets -- Criteria for the simple path property in timed automata -- Hierarchical representations of discrete functions, with application to model checking -- Symbolic verification with periodic sets -- Automatic verification of pipelined microprocessor control -- Using abstractions for the verification of linear hybrid systems -- Decidability of hybrid systems with rectangular differential inclusions -- Suspension automata: A decidable class of hybrid automata -- Verification of context-free timed systems using linear hybrid observers -- On the random walk method for protocol testing -- An automata-theoretic approach to branching-time model checking (Extended abstract) -- Realizability and synthesis of reactive modules -- Model checking of macro processes -- Methodology and system for practical formal verification of reactive hardware -- Modeling and verification of a real life protocol using symbolic model checking -- Verification of a distributed cache memory by using abstractions -- Beyond model checking -- Models whose checks don't explode -- On the automatic computation of network invariants -- Ground temporal logic: A logic for hardware verification -- A hybrid model for reasoning about composed hardware systems -- Composing symbolic trajectory evaluation results -- The completeness of a hardware inference system -- Efficient model checking by automated ordering of transition relation partitions -- The verification problem for safe replaceability -- Formula-dependent equivalence for compositional CTL model checking -- An improved algorithm for the evaluation of fixpoint expressions -- Incremental model checking in the modal mu-calculus -- Performance improvement of state space exploration by regular & differential hashing functions -- Combining partial order reductions with on-the-fly model-checking -- Improving language containment using fairness graphs -- A parallel algorithm for relational coarsest partition problems and its implementation -- Another look at LTL model checking -- The mobility workbench ? A tool for the ?-Calculus -- Compositional semantics of Esterel and verification by compositional reductions -- Model checking using adaptive state and data abstraction -- Automatic verification of timed circuits. 330 $aThis volume contains the proceedings of the 6th Conference on Computer Aided Verification, held at Stanford University in June 1994. The in total 37 included papers were selected in a highly competetive reviewing process from 121 submissions; in total they document many of the most important advances achieved in CAV research and applications since the predecessor conference held in June 1993. The volume is organized in sections on Real-Time Systems, CAV Theory, CAV Applications, Symbolic Verification, Hybrid Systems, Model Checking, Improving Efficiency, and Hardware Verification. 410 0$aLecture Notes in Computer Science,$x0302-9743 ;$v818 606 $aComputers 606 $aSoftware engineering 606 $aComputer logic 606 $aElectronics 606 $aMicroelectronics 606 $aComputer communication systems 606 $aTheory of Computation$3https://scigraph.springernature.com/ontologies/product-market-codes/I16005 606 $aSoftware Engineering/Programming and Operating Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/I14002 606 $aLogics and Meanings of Programs$3https://scigraph.springernature.com/ontologies/product-market-codes/I1603X 606 $aSoftware Engineering$3https://scigraph.springernature.com/ontologies/product-market-codes/I14029 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 606 $aComputer Communication Networks$3https://scigraph.springernature.com/ontologies/product-market-codes/I13022 615 0$aComputers. 615 0$aSoftware engineering. 615 0$aComputer logic. 615 0$aElectronics. 615 0$aMicroelectronics. 615 0$aComputer communication systems. 615 14$aTheory of Computation. 615 24$aSoftware Engineering/Programming and Operating Systems. 615 24$aLogics and Meanings of Programs. 615 24$aSoftware Engineering. 615 24$aElectronics and Microelectronics, Instrumentation. 615 24$aComputer Communication Networks. 676 $a004.0151 702 $aDill$b David L$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a996466265803316 996 $aComputer Aided Verification$9772228 997 $aUNISA