LEADER 07768nam 22007575 450 001 996466222103316 005 20200703143145.0 024 7 $a10.1007/11562948 035 $a(CKB)1000000000213293 035 $a(SSID)ssj0000316403 035 $a(PQKBManifestationID)11273158 035 $a(PQKBTitleCode)TC0000316403 035 $a(PQKBWorkID)10275508 035 $a(PQKB)10577404 035 $a(DE-He213)978-3-540-31969-6 035 $a(MiAaPQ)EBC3067696 035 $a(PPN)123097983 035 $a(EXLCZ)991000000000213293 100 $a20100316d2005 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aAutomated Technology for Verification and Analysis$b[electronic resource] $eThird International Symposium, ATVA 2005, Taipei, Taiwan, October 4-7, 2005, Proceedings /$fedited by Doron A. Peled, Yih-Kuen Tsay 205 $a1st ed. 2005. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2005. 215 $a1 online resource (XII, 508 p.) 225 1 $aProgramming and Software Engineering ;$v3707 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$aPrinted edition: 9783540292098 320 $aIncludes bibliographical references and index. 327 $aKeynote Speeches -- Ranking Abstraction as a Companion to Predicate Abstraction -- Termination and Invariance Analysis of Loops -- Some Perspectives of Infinite-State Verification -- Model Checking -- Verifying Very Large Industrial Circuits Using 100 Processes and Beyond -- A New Reachability Algorithm for Symmetric Multi-processor Architecture -- Comprehensive Verification Framework for Dependability of Self-optimizing Systems -- Exploiting Hub States in Automatic Verification -- Combined Methods -- An Approach for the Verification of SystemC Designs Using AsmL -- Decomposition-Based Verification of Cyclic Workflows -- Timed, Embedded, and Hybrid Systems (I) -- Guaranteed Termination in the Verification of LTL Properties of Non-linear Robust Discrete Time Hybrid Systems -- Computation Platform for Automatic Analysis of Embedded Software Systems Using Model Based Approach -- Quantitative and Qualitative Analysis of Temporal Aspects of Complex Activities -- Automatic Test Case Generation with Region-Related Coverage Annotations for Real-Time Systems -- Abstraction and Reduction Techniques -- Selective Search in Bounded Model Checking of Reachability Properties -- Predicate Abstraction of RTL Verilog Descriptions Using Constraint Logic Programming -- State Space Exploration of Object-Based Systems Using Equivalence Reduction and the Sweepline Method -- Syntactical Colored Petri Nets Reductions -- Decidability and Complexity -- Algorithmic Algebraic Model Checking II: Decidability of Semi-algebraic Model Checking and Its Applications to Systems Biology -- A Static Analysis Using Tree Automata for XML Access Control -- Reasoning About Transfinite Sequences -- Semi-automatic Distributed Synthesis -- Established Formalisms and Standards -- A New Graph of Classes for the Preservation of Quantitative Temporal Constraints -- Comparison of Different Semantics for Time Petri Nets -- Introducing Dynamic Properties with Past Temporal Operators in the B Refinement -- Approximate Reachability for Dead Code Elimination in Esterel??? -- Compositional Verification and Games -- Synthesis of Interface Automata -- Multi-valued Model Checking Games -- Timed, Embedded, and Hybrid Systems (II) -- Model Checking Prioritized Timed Automata -- An MTBDD-Based Implementation of Forward Reachability for Probabilistic Timed Automata -- Protocols Analysis, Case Studies, and Tools -- An EFSM-Based Intrusion Detection System for Ad Hoc Networks -- Modeling and Verification of a Telecommunication Application Using Live Sequence Charts and the Play-Engine Tool -- Formal Construction and Verification of Home Service Robots: A Case Study -- Model Checking Real Time Java Using Java PathFinder -- Infinite-State and Parameterized Systems -- Using Parametric Automata for the Verification of the Stop-and-Wait Class of Protocols -- Flat Acceleration in Symbolic Model Checking -- Flat Counter Automata Almost Everywhere!. 330 $aThe Automated Technology for Veri?cation and Analysis (ATVA) international symposium series was initiated in 2003, responding to a growing interest in formal veri?cation spurred by the booming IT industry, particularly hardware design and manufacturing in East Asia. Its purpose is to promote research on automated veri?cation and analysis in the region by providing a forum for int- action between the regional and the international research/industrial commu- ties of the ?eld. ATVA 2005, the third of the ATVA series, was held in Taipei, Taiwan, October 4?7, 2005. The main theme of the symposium encompasses - sign, complexities, tools, and applications of automated methods for veri?cation and analysis. The symposium was co-located and had a two-day overlap with FORTE 2005, which was held October 2?5, 2005. We received a total of 95 submissions from 17 countries. Each submission was assigned to three Program Committee members, who were helped by their subreviewers, for rigorous and fair evaluation. The ?nal deliberation by the P- gram Committee was conducted over email for a duration of about 10 days after nearly all review reports had been collected. In the end, 33 papers were - lectedforinclusionintheprogram.ATVA2005hadthreekeynotespeechesgiven respectively by Amir Pnueli (joint with FORTE 2005), Zohar Manna, and Wo- gang Thomas. The main symposium was preceded by a tutorial day, consisting of three two-hour lectures given also by the keynote speakers. 410 0$aProgramming and Software Engineering ;$v3707 606 $aComputer-aided engineering 606 $aComputer logic 606 $aComputer communication systems 606 $aSpecial purpose computers 606 $aSoftware engineering 606 $aProgramming languages (Electronic computers) 606 $aComputer-Aided Engineering (CAD, CAE) and Design$3https://scigraph.springernature.com/ontologies/product-market-codes/I23044 606 $aLogics and Meanings of Programs$3https://scigraph.springernature.com/ontologies/product-market-codes/I1603X 606 $aComputer Communication Networks$3https://scigraph.springernature.com/ontologies/product-market-codes/I13022 606 $aSpecial Purpose and Application-Based Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/I13030 606 $aSoftware Engineering$3https://scigraph.springernature.com/ontologies/product-market-codes/I14029 606 $aProgramming Languages, Compilers, Interpreters$3https://scigraph.springernature.com/ontologies/product-market-codes/I14037 615 0$aComputer-aided engineering. 615 0$aComputer logic. 615 0$aComputer communication systems. 615 0$aSpecial purpose computers. 615 0$aSoftware engineering. 615 0$aProgramming languages (Electronic computers). 615 14$aComputer-Aided Engineering (CAD, CAE) and Design. 615 24$aLogics and Meanings of Programs. 615 24$aComputer Communication Networks. 615 24$aSpecial Purpose and Application-Based Systems. 615 24$aSoftware Engineering. 615 24$aProgramming Languages, Compilers, Interpreters. 676 $a620.00420285 702 $aPeled$b Doron A$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aTsay$b Yih-Kuen$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a996466222103316 996 $aAutomated Technology for Verification and Analysis$9772478 997 $aUNISA