LEADER 04913nam 22008415 450 001 996466116403316 005 20230406064252.0 010 $a3-540-39097-9 024 7 $a10.1007/11847083 035 $a(CKB)1000000000283894 035 $a(SSID)ssj0000318343 035 $a(PQKBManifestationID)11239139 035 $a(PQKBTitleCode)TC0000318343 035 $a(PQKBWorkID)10328353 035 $a(PQKB)11417680 035 $a(DE-He213)978-3-540-39097-8 035 $a(MiAaPQ)EBC3068126 035 $a(PPN)123137993 035 $a(EXLCZ)991000000000283894 100 $a20100301d2006 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation$b[electronic resource] $e16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings /$fedited by Johan Vounckx, Nadine Azemard, Philippe Maurine 205 $a1st ed. 2006. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2006. 215 $a1 online resource (XVI, 677 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4148 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-39094-4 320 $aIncludes bibliographical references and index. 327 $aSession 1 ? High-Level Design -- Session 2 ? Power Estimation / Modeling -- Session 3 ? Memory and Register Files -- Session 4 ? Low-Power Digital Circuits -- Session 5 ? Busses and Interconnects -- Session 6 ? Low Power Techniques -- Session 7 ? Applications and SoC Design -- Session 8 ? Modeling -- Session 9 ? Digital Circuits -- Session 10 ? Reconfigurable and Programmable Devices -- Poster 1 -- Poster 2 -- Poster 3 -- Keynotes -- Industrial Session. 330 $aWelcome to the proceedings of PATMOS 2006, the 16th in a series of international workshops. PATMOS 2006 was organized by LIRMM with CAS technical - sponsorship and CEDA sponsorship. Over the years, the PATMOS workshop has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design methodologies, and tools required for the development of upcoming generations of integrated circuits and systems. The technical program of PATMOS 2006 contained state-of-the-art technical contributions, three invited talks, a special session on hearing-aid design, and an embedded tutorial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 64 papers presented at PATMOS. The papers were organized into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4148 606 $aComputer science 606 $aLogic design 606 $aMicroprocessors 606 $aComputer architecture 606 $aElectronic digital computers?Evaluation 606 $aComputer arithmetic and logic units 606 $aComputer storage devices 606 $aMemory management (Computer science) 606 $aTheory of Computation 606 $aLogic Design 606 $aProcessor Architectures 606 $aSystem Performance and Evaluation 606 $aArithmetic and Logic Structures 606 $aComputer Memory Structure 615 0$aComputer science. 615 0$aLogic design. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 0$aElectronic digital computers?Evaluation. 615 0$aComputer arithmetic and logic units. 615 0$aComputer storage devices. 615 0$aMemory management (Computer science). 615 14$aTheory of Computation. 615 24$aLogic Design. 615 24$aProcessor Architectures. 615 24$aSystem Performance and Evaluation. 615 24$aArithmetic and Logic Structures. 615 24$aComputer Memory Structure. 676 $a621.395 686 $aSS 4800$2rvk 702 $aVounckx$b Johan$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aAzemard$b Nadine$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aMaurine$b Philippe$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a996466116403316 996 $aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation$9772134 997 $aUNISA