LEADER 07826nam 22008655 450 001 996466103503316 005 20230221131820.0 010 $a3-540-73625-5 024 7 $a10.1007/978-3-540-73625-7 035 $a(CKB)1000000000490536 035 $a(SSID)ssj0000317393 035 $a(PQKBManifestationID)11231551 035 $a(PQKBTitleCode)TC0000317393 035 $a(PQKBWorkID)10294261 035 $a(PQKB)10507255 035 $a(DE-He213)978-3-540-73625-7 035 $a(MiAaPQ)EBC3061740 035 $a(MiAaPQ)EBC6451352 035 $a(PPN)123163749 035 $a(EXLCZ)991000000000490536 100 $a20100301d2007 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aEmbedded Computer Systems: Architectures, Modeling, and Simulation$b[electronic resource] $e7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings /$fedited by Stamatis Vassiliadis, Mladen Berekovic, Timo D. Hämäläinen 205 $a1st ed. 2007. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2007. 215 $a1 online resource (XVII, 470 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4599 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-73622-0 327 $aKeynotes -- Software Is the Answer But What Is the Question? -- Integrating VLIW Processors with a Network on Chip -- System Modeling and Simulation -- Communication Architecture Simulation on the Virtual Synchronization Framework -- A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems -- Performance Evaluation of Memory Management Configurations in Linux for an OS-Level Design Space Exploration -- SC2SCFL: Automated SystemC to Translation -- VLSI Architectures -- Model and Validation of Block Cleaning Cost for Flash Memory -- VLSI Architecture for MRF Based Stereo Matching -- Low-Power Twiddle Factor Unit for FFT Computation -- Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors -- Scheduling & Programming Models -- An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code -- Improving TriMedia Cache Performance by Profile Guided Code Reordering -- A Streaming Machine Description and Programming Model -- Multi-processor Architectures -- Mapping and Performance Evaluation for Heterogeneous MP-SoCs Via Packing -- Strategies for Compiling ?TC to Novel Chip Multiprocessors -- Image Quantisation on a Massively Parallel Embedded Processor -- Stream Image Processing on a Dual-Core Embedded System -- Reconfigurable Architectures -- MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing -- FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder -- Evaluating Large System-on-Chip on Multi-FPGA Platform -- Design Space Exploration -- Efficiency Measures for Multimedia SOCs -- On-Chip Bus Modeling for Power and Performance Estimation -- A Framework Introducing Model Reversibility in SoC Design Space Exploration -- Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration -- Processor Components -- Resource Conflict Detection in Simulation of Function Unit Pipelines -- A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing -- High-Bandwidth Address Generation Unit -- An IP Core for Embedded Java Systems -- Embedded Processors -- Parallel Memory Architecture for TTA Processor -- A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size -- Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction -- A Study of Energy Saving in Customizable Processors -- SoC for SDR -- Trends in Low Power Handset Software Defined Radio -- Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals -- Area Efficient Fully Programmable Baseband Processors -- The Next Generation Challenge for Software Defined Radio -- Design Methodology for Software Radio Systems -- Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC -- A Comparative Study of Different FFT Architectures for Software Defined Radio -- Wireless Sensors -- Design of 100 ?W Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring -- Tool-Aided Design and Implementation of Indoor Surveillance Wireless Sensor Network -- System Architecture Modeling of an UWB Receiver for Wireless Sensor Network -- An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks -- SensorOS: A New Operating System for Time Critical WSN Applications -- Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks -- k ?+? Neigh: An Energy Efficient Topology Control for Wireless Sensor Networks. 330 $aStamatis Vassiliadis established the SAMOS workshop in the year 2001?an event which combines his devotion to computer engineering and his pride for Samos, the island where he was born. The quiet and inspiring northern mo- tainside of this Mediterranean island together with his enthusiasm and warmth created a unique atmosphere that made this event so successful. Stamatis V- siliadis passed away on Saturday, April 7, 2007. The research community wants to express its gratitude to him for the creation of the SAMOS workshop, which will not be the same without him. We would like to dedicate this proceedings volume to the memory of Stamatis Vassiliadis. The SAMOS workshop is an international gathering of highly quali?ed - searchers from academia and industry, sharing their ideas during a 3-day lively discussion.Theworkshopmeetingisoneoftwocolocatedevents?theotherevent being the IC-SAMOS. The workshop is unique in the sense that not only solved research problems are presented and discussed but also (partly) unsolved pr- lems and in-depth topical reviews can be unleashed in the scienti?c arena. C- sequently, the workshop provides the participants with an environment where collaboration rather than competition is fostered. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4599 606 $aComputer science 606 $aComputers 606 $aMicroprocessors 606 $aComputer architecture 606 $aComputer networks 606 $aElectronic digital computers?Evaluation 606 $aComputer systems 606 $aTheory of Computation 606 $aComputer Hardware 606 $aProcessor Architectures 606 $aComputer Communication Networks 606 $aSystem Performance and Evaluation 606 $aComputer System Implementation 615 0$aComputer science. 615 0$aComputers. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 0$aComputer networks. 615 0$aElectronic digital computers?Evaluation. 615 0$aComputer systems. 615 14$aTheory of Computation. 615 24$aComputer Hardware. 615 24$aProcessor Architectures. 615 24$aComputer Communication Networks. 615 24$aSystem Performance and Evaluation. 615 24$aComputer System Implementation. 676 $a004.22 686 $aDAT 260f$2stub 686 $aSS 4800$2rvk 702 $aHämäläinen$b Timo D. 702 $aBerekovicÌ$b Mladen 702 $aVassiliadis$b Stamatis 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bUtOrBLW 906 $aBOOK 912 $a996466103503316 996 $aEmbedded Computer Systems: Architectures, Modeling, and Simulation$9772127 997 $aUNISA