LEADER 05462nam 22007575 450 001 996466086203316 005 20200707021029.0 010 $a3-540-70655-0 024 7 $a10.1007/BFb0021709 035 $a(CKB)1000000000233972 035 $a(SSID)ssj0000322362 035 $a(PQKBManifestationID)11246289 035 $a(PQKBTitleCode)TC0000322362 035 $a(PQKBWorkID)10288441 035 $a(PQKB)11588025 035 $a(DE-He213)978-3-540-70655-7 035 $a(PPN)15523353X 035 $a(EXLCZ)991000000000233972 100 $a20121227d1993 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aCorrect Hardware Design and Verification Methods$b[electronic resource] $eIFIP WG 10.2 Advanced Research Working Conference, CHARME'93, Arles, France, May 24-26, 1993. Proceedings /$fedited by George J. Milne, Laurence Pierre 205 $a1st ed. 1993. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d1993. 215 $a1 online resource (IX, 275 p.) 225 1 $aLecture Notes in Computer Science,$x0302-9743 ;$v683 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-56778-X 327 $aA graph-based method for timing diagrams representation and verification -- A Petri Net approach for the analysis of VHDL descriptions -- Temporal analysis of time bounded digital systems -- Strongly-typed theory of structures and behaviours -- Verification and diagnosis of digital systems by ternary reasoning -- Logic verification of incomplete functions and design error location -- A methodology for system-level design for verifiability -- Algebraic models and the correctness of microprocessors -- Combining symbolic evaluation and object oriented approach for verifying processor-like architectures at the RT-level -- A theory of generic interpreters -- Towards verifying large(r) systems: A strategy and an experiment -- Advancements in symbolic traversal techniques -- Automatic verification of speed-independent circuit designs using the Circal system -- Correct compilation of specifications to deterministic asynchronous circuits -- DDD-FM9001: Derivation of a verified microprocessor -- Calculational derivation of a counter with bounded response time -- Towards a provably correct hardware implementation of occam -- Rewriting with constraints in T-ruby -- Embedding hardware verification within a commercial design framework -- An approach to formalization of data flow graphs. 330 $aThese proceedings contain the papers presented at the Advanced Research Working Conference on Correct Hardware Design Methodologies, held in Arles, France, in May 1993, and organized by the ESPRIT Working Group 6018 CHARME-2and the Universit de Provence, Marseille, in cooperation with IFIP Working Group 10.2. Formal verification is emerging as a plausible alternative to exhaustive simulation for establishing correct digital hardware designs. The validation of functional and timing behavior is a major bottleneck in current VLSI design systems, slowing the arrival of products in the marketplace with its associated increase in cost. From being a predominantly academic area of study until a few years ago, formal design and verification techniques are now beginning to migrate into industrial use. As we are now witnessing an increase in activity in this area in both academia and industry, the aim of this working conference was to bring together researchers and users from both communities. 410 0$aLecture Notes in Computer Science,$x0302-9743 ;$v683 606 $aComputers 606 $aComputer hardware 606 $aMicroprogramming  606 $aArithmetic and logic units, Computer 606 $aComputer memory systems 606 $aInput-output equipment (Computers) 606 $aTheory of Computation$3https://scigraph.springernature.com/ontologies/product-market-codes/I16005 606 $aComputer Hardware$3https://scigraph.springernature.com/ontologies/product-market-codes/I1200X 606 $aControl Structures and Microprogramming$3https://scigraph.springernature.com/ontologies/product-market-codes/I12018 606 $aArithmetic and Logic Structures$3https://scigraph.springernature.com/ontologies/product-market-codes/I12026 606 $aMemory Structures$3https://scigraph.springernature.com/ontologies/product-market-codes/I12034 606 $aInput/Output and Data Communications$3https://scigraph.springernature.com/ontologies/product-market-codes/I12042 615 0$aComputers. 615 0$aComputer hardware. 615 0$aMicroprogramming . 615 0$aArithmetic and logic units, Computer. 615 0$aComputer memory systems. 615 0$aInput-output equipment (Computers). 615 14$aTheory of Computation. 615 24$aComputer Hardware. 615 24$aControl Structures and Microprogramming. 615 24$aArithmetic and Logic Structures. 615 24$aMemory Structures. 615 24$aInput/Output and Data Communications. 676 $a621.39/2 702 $aMilne$b George J$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aPierre$b Laurence$4edt$4http://id.loc.gov/vocabulary/relators/edt 712 12$aCHARME '93 906 $aBOOK 912 $a996466086203316 996 $aCorrect Hardware Design and Verification Methods$9772373 997 $aUNISA