LEADER 06099nam 22007455 450 001 996466078003316 005 20230117220036.0 010 $a3-540-47572-9 024 7 $a10.1007/3-540-56496-9 035 $a(CKB)1000000000233940 035 $a(SSID)ssj0000322077 035 $a(PQKBManifestationID)11243175 035 $a(PQKBTitleCode)TC0000322077 035 $a(PQKBWorkID)10281384 035 $a(PQKB)11327162 035 $a(DE-He213)978-3-540-47572-9 035 $a(PPN)155216422 035 $a(EXLCZ)991000000000233940 100 $a20121227d1993 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aComputer Aided Verification$b[electronic resource] $eFourth International Workshop, CAV '92, Montreal, Canada, June 29 - July 1, 1992. Proceedings /$fedited by Gregor von Bochmann, David K. Probst 205 $a1st ed. 1993. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d1993. 215 $a1 online resource (IX, 426 p.) 225 1 $aLecture Notes in Computer Science,$x0302-9743 ;$v663 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-56496-9 327 $aComputer-hindered verification (humans can do it too) -- Modular abstractions for verifying real-time distributed systems -- Layering techniques for development of parallel systems -- Efficient local correctness checking -- Mechanical verification of concurrent systems with TLA -- Using a theorem prover for reasoning about concurrent algorithms -- Verifying a logic synthesis tool in Nuprl: A case study in software verification -- Higher-level specification and verification with BDDs -- Symbolic bisimulation minimisation -- Towards a verification technique for large synchronous circuits -- Verifying timed behavior automata with nonbinary delay constraints -- Timing verification by successive approximation -- A verification strategy for timing constrained systems -- Using unfoldings to avoid the state explosion problem in the verification of asynchronous circuits -- State space caching revisited -- Verification in process algebra of the distributed control of track vehicles?A case study -- Design verification of a microprocessor using branching time regular temporal logic -- A case study in safety-critical design -- Automatic reduction in CTL compositional model checking -- Compositional model checking for linear-time temporal logic -- Property preserving simulations -- Verification with real-time COSPAN -- Model-checking for real-time systems specified in Lotos -- Decidability of bisimulation equivalences for parallel timer processes -- A proof assistant for symbolic model-checking -- Tableau recycling -- Crocos: An integrated environment for interactive verification of SDL specifications -- Verifying general safety and liveness properties with integer programming -- Generating diagnostic information for behavioral preorders -- A verification procedure via invariant for extended communicating finite-state machines -- Efficient ?-regular language containment -- Faster model checking for the modal Mu-Calculus. 330 $aThis volume gives the proceedings of the Fourth Workshop on Computer-Aided Verification (CAV '92), held in Montreal, June 29 - July 1, 1992. The objective of this series of workshops is to bring together researchers and practitioners interested in the development and use of methods, tools and theories for the computer-aided verification of concurrent systems. The workshops provide an opportunity for comparing various verification methods and practical tools that can be used to assist the applications designer. Emphasis is placed on new research results and the application of existing results to real verification problems. The volume contains 31 papers selected from 75 submissions. These are organized into parts on reduction techniques, proof checking, symbolic verification, timing verification, partial-order approaches, case studies, model and proof checking, and other approaches. The volume starts with an invited lecture by Leslie Lamport entitled "Computer-hindered verification (humans can do it too)". 410 0$aLecture Notes in Computer Science,$x0302-9743 ;$v663 606 $aComputer logic 606 $aOperating systems (Computers) 606 $aSoftware engineering 606 $aElectronics 606 $aMicroelectronics 606 $aMathematical logic 606 $aLogics and Meanings of Programs$3https://scigraph.springernature.com/ontologies/product-market-codes/I1603X 606 $aOperating Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/I14045 606 $aSoftware Engineering/Programming and Operating Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/I14002 606 $aSoftware Engineering$3https://scigraph.springernature.com/ontologies/product-market-codes/I14029 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 606 $aMathematical Logic and Foundations$3https://scigraph.springernature.com/ontologies/product-market-codes/M24005 615 0$aComputer logic. 615 0$aOperating systems (Computers). 615 0$aSoftware engineering. 615 0$aElectronics. 615 0$aMicroelectronics. 615 0$aMathematical logic. 615 14$aLogics and Meanings of Programs. 615 24$aOperating Systems. 615 24$aSoftware Engineering/Programming and Operating Systems. 615 24$aSoftware Engineering. 615 24$aElectronics and Microelectronics, Instrumentation. 615 24$aMathematical Logic and Foundations. 676 $a005.1015113 702 $aBochmann$b Gregor von$f1941-$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aProbst$b David K$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a996466078003316 996 $aComputer Aided Verification$93027789 997 $aUNISA