LEADER 05281nam 22008175 450 001 996466048203316 005 20230406051836.0 010 $a3-540-77560-9 024 7 $a10.1007/978-3-540-77560-7 035 $a(CKB)1000000000490639 035 $a(SSID)ssj0000318107 035 $a(PQKBManifestationID)11292459 035 $a(PQKBTitleCode)TC0000318107 035 $a(PQKBWorkID)10307795 035 $a(PQKB)11062053 035 $a(DE-He213)978-3-540-77560-7 035 $a(MiAaPQ)EBC3062131 035 $a(MiAaPQ)EBC6386421 035 $a(PPN)123743338 035 $a(EXLCZ)991000000000490639 100 $a20100301d2008 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aHigh Performance Embedded Architectures and Compilers$b[electronic resource] $eThird International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /$fedited by Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer 205 $a1st ed. 2008. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2008. 215 $a1 online resource (XIII, 400 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4917 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-77559-5 320 $aIncludes bibliographical references and index. 327 $aInvited Program -- Supercomputing for the Future, Supercomputing from the Past (Keynote) -- I Multithreaded and Multicore Processors -- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing -- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect -- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE -- IIa Reconfigurable - ASIP -- BRAM-LUT Tradeoff on a Polymorphic DES Design -- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array -- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP -- IIb Compiler Optimizations -- Fast Bounds Checking Using Debug Register -- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis -- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems -- III Industrial Processors and Application Parallelization -- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions -- Experiences with Parallelizing a Bio-informatics Program on the Cell BE -- Drug Design Issues on the Cell BE -- IV Power-Aware Techniques -- Coffee: COmpiler Framework for Energy-Aware Exploration -- Integrated CPU Cache Power Management in Multiple Clock Domain Processors -- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation -- V High-Performance Processors -- The Significance of Affectors and Affectees Correlations for Branch Prediction -- Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator -- LPA: A First Approach to the Loop Processor Architecture -- VI Profiles: Collection and Analysis -- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm -- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy -- Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior -- VII Optimizing Memory Performance -- MLP-Aware Dynamic Cache Partitioning -- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture -- Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory -- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4917 606 $aComputer arithmetic and logic units 606 $aCompilers (Computer programs) 606 $aComputer systems 606 $aMicroprocessors 606 $aComputer architecture 606 $aComputer input-output equipment 606 $aLogic design 606 $aArithmetic and Logic Structures 606 $aCompilers and Interpreters 606 $aComputer System Implementation 606 $aProcessor Architectures 606 $aInput/Output and Data Communications 606 $aLogic Design 615 0$aComputer arithmetic and logic units. 615 0$aCompilers (Computer programs). 615 0$aComputer systems. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 0$aComputer input-output equipment. 615 0$aLogic design. 615 14$aArithmetic and Logic Structures. 615 24$aCompilers and Interpreters. 615 24$aComputer System Implementation. 615 24$aProcessor Architectures. 615 24$aInput/Output and Data Communications. 615 24$aLogic Design. 676 $a004.22 702 $aStenström$b Per 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bUtOrBLW 906 $aBOOK 912 $a996466048203316 996 $aHigh Performance Embedded Architectures and Compilers$9772079 997 $aUNISA