LEADER 09997nam 22009255 450 001 996465995703316 005 20230406054950.0 010 $a3-540-74442-8 024 7 $a10.1007/978-3-540-74442-9 035 $a(CKB)1000000000490694 035 $a(SSID)ssj0000318340 035 $a(PQKBManifestationID)11266632 035 $a(PQKBTitleCode)TC0000318340 035 $a(PQKBWorkID)10310235 035 $a(PQKB)10225325 035 $a(DE-He213)978-3-540-74442-9 035 $a(MiAaPQ)EBC3063424 035 $a(MiAaPQ)EBC337392 035 $a(MiAaPQ)EBC6699191 035 $a(Au-PeEL)EBL337392 035 $a(CaONFJC)MIL135360 035 $a(OCoLC)808680889 035 $a(Au-PeEL)EBL6699191 035 $a(PPN)123164451 035 $a(EXLCZ)991000000000490694 100 $a20100301d2007 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation$b[electronic resource] $e17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings /$fedited by Nadine Azemard, Lars Svensson 205 $a1st ed. 2007. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2007. 215 $a1 online resource (XIV, 586 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4644 300 $aIncludes index. 311 $a3-540-74441-X 320 $aIncludes bibliographical references and index. 327 $aSession 1 - High-Level Design (1) -- System-Level Application-Specific NoC Design for Network and Multimedia Applications -- Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements -- A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms -- An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture -- Session 2 - Low Power Design Techniques -- Template Vertical Dictionary-Based Program Compression Scheme on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs -- Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports -- The Design and Implementation of a Power Efficient Embedded SRAM -- Session 3 - Low Power Analog Circuits -- Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN -- Settling Time Minimization of Operational Amplifiers -- Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs -- Session 4 - Statistical Static Timing Analysis -- Computation of Joint Timing Yield of Sequential Networks Considering Process Variations -- A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation -- A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits -- Session 5 - Power Modeling and Optimization -- A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect -- Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components -- Logic Style Comparison for Ultra Low Power Operation in 65nm Technology -- Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation -- Session 6 - Low Power Routing Optimization -- Clock Distribution Techniques for Low-EMI Design -- Crosstalk Waveform Modeling Using Wave Fitting -- Weakness Identification for Effective Repair of Power Distribution Network -- New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses -- On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects -- Session 7 - High Level Design (2) -- Soft Error-Aware Power Optimization Using Gate Sizing -- Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices -- RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating -- Functional Verification of Low Power Designs at RTL -- XEEMU: An Improved XScale Power Simulator -- Session 8 - Security and Asynchronous Design -- Low Power Elliptic Curve Cryptography -- Design and Test of Self-checking Asynchronous Control Circuit -- An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips -- Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA -- Session 9 - Low Power Applications -- Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform -- The Energy Scalability of Wavelet-Based, Scalable Video Decoding -- Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption -- Poster 1 - Modeling and Optimization -- Exploiting Input Variations for Energy Reduction -- A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates -- Static Power Consumption in CMOS Gates Using Independent Bodies -- Moderate Inversion: Highlights for Low Voltage Design -- On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems -- Semi Custom Design: A Case Study on SIMD Shufflers -- Poster 2 - High Level Design -- Optimization for Real-Time Systems with Non-convex Power Versus Speed Models -- Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS -- A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits -- Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates -- A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning -- Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems -- Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate -- Poster 3 - Low Power Techniques and Applications -- A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations -- Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data -- Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply -- Low-Power Digital Filtering Based on the Logarithmic Number System -- A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling -- Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers -- Keynotes -- Design and Industrialization Challenges of Memory Dominated SOCs -- Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies -- Analog Power Modelling -- Industrial Session - Design Challenges in Real-Life Projects -- Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms -- System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters. 330 $ath Welcome to the proceedings of PATMOS 2007, the 17 in a series of international workshops. PATMOS 2007 was organized by Chalmers University of Technology with IEEE Sweden Chapter of the Solid-State Circuit Society technical - sponsorship and IEEE CEDA sponsorship. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2007 consisted of state-of-the-art te- nical contributions, three invited talks and an industrial session on design challenges in real-life projects. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on m- eling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert - viewers, selected the 55 papers presented at PATMOS. The papers were organized into 9 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4644 606 $aLogic design 606 $aMicroprocessors 606 $aComputer architecture 606 $aElectronic digital computers?Evaluation 606 $aComputer arithmetic and logic units 606 $aComputer storage devices 606 $aMemory management (Computer science) 606 $aElectronic circuits 606 $aLogic Design 606 $aProcessor Architectures 606 $aSystem Performance and Evaluation 606 $aArithmetic and Logic Structures 606 $aComputer Memory Structure 606 $aElectronic Circuits and Systems 615 0$aLogic design. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 0$aElectronic digital computers?Evaluation. 615 0$aComputer arithmetic and logic units. 615 0$aComputer storage devices. 615 0$aMemory management (Computer science). 615 0$aElectronic circuits. 615 14$aLogic Design. 615 24$aProcessor Architectures. 615 24$aSystem Performance and Evaluation. 615 24$aArithmetic and Logic Structures. 615 24$aComputer Memory Structure. 615 24$aElectronic Circuits and Systems. 676 $a621.395 702 $aAzemard$b Nadine$f1963- 702 $aSvensson$b Lars$f1960- 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a996465995703316 996 $aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation$9772134 997 $aUNISA LEADER 03416nam 22006615 450 001 9910255285903321 005 20251116173032.0 010 $a9783319547800 010 $a3319547801 024 7 $a10.1007/978-3-319-54780-0 035 $a(CKB)3710000001393626 035 $a(DE-He213)978-3-319-54780-0 035 $a(MiAaPQ)EBC4871086 035 $a(PPN)259468827 035 $a(Perlego)3497104 035 $a(EXLCZ)993710000001393626 100 $a20170602d2017 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 14$aThe 2015 UK General Election and the 2016 EU Referendum $eTowards a Democracy of the Spectacle /$fby Ian R. Lamond, Chelsea Reid 205 $a1st ed. 2017. 210 1$aCham :$cSpringer International Publishing :$cImprint: Palgrave Macmillan,$d2017. 215 $a1 online resource (XVI, 88 p.) 311 08$a9783319547794 311 08$a3319547798 320 $aIncludes bibliographical references and index. 327 $aIntroduction -- PART I -- 1: Bringing together political communication and critical event studies -- 2: Models of democracy -- PART II -- 3: The 2015 UK General Election -- 4: The 2016 EU Referendum -- 5: Conclusion -- Annex: Beyond the UK. 330 $aThis book brings together the established field of political communication and the emerging field of critical event studies to develop new questions and approaches. Using this combined framework, it reflects upon how we should understand the expression of democratic participation in mainstream mass media during the 2015 UK General Election and the 2016 referendum on Britain's membership of the EU. Are we now living in an era where democratic participation is much more concerned with spectacle rather than substantive debate? The book addresses this conceptual journey and reflects on differing models of democratic participation, before applying that framework to the two identified case studies. Finally, the authors consider what it means to be living in a period of democratic spectacle, where political events have become evental politics. The book will be of use to students and scholars across the fields of political science and culture and media studies, as well as wide readers interested in the current issues facing British politics. . 606 $aCommunication in politics 606 $aElections 606 $aEurope$xPolitics and government 606 $aJournalism 606 $aPolitical sociology 606 $aPolitical Communication 606 $aElectoral Politics 606 $aEuropean Politics 606 $aJournalism 606 $aPolitical Sociology 615 0$aCommunication in politics. 615 0$aElections. 615 0$aEurope$xPolitics and government. 615 0$aJournalism. 615 0$aPolitical sociology. 615 14$aPolitical Communication. 615 24$aElectoral Politics. 615 24$aEuropean Politics. 615 24$aJournalism. 615 24$aPolitical Sociology. 676 $a320.014 700 $aLamond$b Ian R.$4aut$4http://id.loc.gov/vocabulary/relators/aut$00 702 $aReid$b Chelsea$4aut$4http://id.loc.gov/vocabulary/relators/aut 906 $aBOOK 912 $a9910255285903321 996 $aThe 2015 UK General Election and the 2016 EU Referendum$92177082 997 $aUNINA