LEADER 05071nam 22007815 450 001 996465983903316 005 20230619182023.0 010 $a3-642-36157-9 024 7 $a10.1007/978-3-642-36157-9 035 $a(CKB)3400000000102980 035 $a(SSID)ssj0000880021 035 $a(PQKBManifestationID)11509150 035 $a(PQKBTitleCode)TC0000880021 035 $a(PQKBWorkID)10873609 035 $a(PQKB)10409838 035 $a(DE-He213)978-3-642-36157-9 035 $a(MiAaPQ)EBC3068803 035 $a(PPN)168329840 035 $a(EXLCZ)993400000000102980 100 $a20130107d2013 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation$b[electronic resource] $e22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers /$fedited by José L. Ayala, Delong Shang, Alex Yakovlev 205 $a1st ed. 2013. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2013. 215 $a1 online resource (IX, 258 p. 150 illus.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v7606 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-642-36156-0 320 $aIncludes bibliographical references and index. 327 $aSleep-Transistor Based Power-Gating Tradeoff Analyses -- Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level -- Non-invasive Power Simulation at System-Level with SystemC -- A Standard Cell Optimization Method for Near-Threshold Voltage Operations -- An Extended Metastability Simulation Method for Synchronizer Characterization -- Phase Space Based NBTI Model -- Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths -- Noise Margin Based Library Optimization Considering Variability in Sub-threshold -- TCP Window Based DVFS for Low Power Network Controller SoC -- A Generic Architecture for Robust Asynchronous Communication Links -- Direct Statistical Simulation of Timing Properties in Sequential Circuits -- On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture -- Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications -- Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor -- Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation -- Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines -- Dynamic Power Management of a Computer with Self Power-Managed Components -- Case Studies of Logical Computation on Stochastic Bit Streams. 330 $aThis book constitutes the refereed proceedings of the 22nd International Conference on Integrated Circuit and System Design, PATMOS 2012, held in Newcastle, UK Spain, in September 2012. The 25 revised full papers presented were carefully reviewed and selected from numerous submissions. The paper feature emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGAs. The technical program focus on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v7606 606 $aElectronic digital computers?Evaluation 606 $aComputer simulation 606 $aComputer networks 606 $aComputer hardware description languages 606 $aLogic design 606 $aCompilers (Computer programs) 606 $aSystem Performance and Evaluation 606 $aComputer Modelling 606 $aComputer Communication Networks 606 $aRegister-Transfer-Level Implementation 606 $aLogic Design 606 $aCompilers and Interpreters 615 0$aElectronic digital computers?Evaluation. 615 0$aComputer simulation. 615 0$aComputer networks. 615 0$aComputer hardware description languages. 615 0$aLogic design. 615 0$aCompilers (Computer programs). 615 14$aSystem Performance and Evaluation. 615 24$aComputer Modelling. 615 24$aComputer Communication Networks. 615 24$aRegister-Transfer-Level Implementation. 615 24$aLogic Design. 615 24$aCompilers and Interpreters. 676 $a004.24 702 $aAyala$b José L$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aShang$b Delong$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aYakovlev$b Alex$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a996465983903316 996 $aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation$9772134 997 $aUNISA