LEADER 06554nam 22008655 450 001 996465976603316 005 20230221012850.0 010 $a1-280-93841-2 010 $a9786610938414 010 $a3-540-72521-0 024 7 $a10.1007/978-3-540-72521-3 035 $a(CKB)1000000000478500 035 $a(EBL)3061505 035 $a(SSID)ssj0000189196 035 $a(PQKBManifestationID)11168144 035 $a(PQKBTitleCode)TC0000189196 035 $a(PQKBWorkID)10173821 035 $a(PQKB)11599547 035 $a(DE-He213)978-3-540-72521-3 035 $a(MiAaPQ)EBC3061505 035 $a(MiAaPQ)EBC6280888 035 $a(PPN)12316236X 035 $a(EXLCZ)991000000000478500 100 $a20100301d2007 u| 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aLanguages and Compilers for Parallel Computing$b[electronic resource] $e19th International Workshop, LCPC 2006, New Orleans, LA, USA, November 2-4, 2006, Revised Papers /$fedited by Gheorghe Almási, Calin Cascaval, Peng Wu 205 $a1st ed. 2007. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2007. 215 $a1 online resource (373 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4382 300 $aDescription based upon print version of record. 311 $a3-540-72520-2 320 $aIncludes bibliographical references and index. 327 $aKeynote I -- Compilation Techniques for Partitioned Global Address Space Languages -- Session 1: Programming Models -- Can Transactions Enhance Parallel Programs? -- Design and Use of htalib ? A Library for Hierarchically Tiled Arrays -- SP@CE - An SP-Based Programming Model for Consumer Electronics Streaming Applications -- Session 2: Code Generation -- Data Pipeline Optimization for Shared Memory Multiple-SIMD Architecture -- Dependence-Based Code Generation for a CELL Processor -- Expression and Loop Libraries for High-Performance Code Synthesis -- Applying Code Specialization to FFT Libraries for Integral Parameters -- Session 3: Parallelism -- A Characterization of Shared Data Access Patterns in UPC Programs -- Exploiting Speculative Thread-Level Parallelism in Data Compression Applications -- On Control Signals for Multi-Dimensional Time -- Keynote II -- The Berkeley View: A New Framework and a New Platform for Parallel Research -- Session 4: Compilation Techniques -- An Effective Heuristic for Simple Offset Assignment with Variable Coalescing -- Iterative Compilation with Kernel Exploration -- Quantifying Uncertainty in Points-To Relations -- Session 5: Data Structures -- Cache Behavior Modelling for Codes Involving Banded Matrices -- Tree-Traversal Orientation Analysis -- UTS: An Unbalanced Tree Search Benchmark -- Session 6: Register Allocation -- Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files -- Optimal Bitwise Register Allocation Using Integer Linear Programming -- Register Allocation: What Does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How -- Session 7: Memory Management -- Custom Memory Allocation for Free -- Optimizing the Use of Static Buffers for DMA on a CELL Chip -- Runtime Address Space Computation for SDSM Systems -- A Static Heap Analysis for Shape and Connectivity: Unified Memory Analysis: The Base Framework. 330 $aThe 19th Workshop on Languages and Compilers for Parallel Computing was heldinNovember2006inNewOrleans,LouisianaUSA.Morethan40researchers from around the world gathered together to present their latest results and to exchange ideas on topics ranging from parallel programming models, code generation,compilationtechniques,paralleldatastructureandparallelexecution models,toregisterallocationandmemorymanagementinparallelenvironments. Out of the 49 paper submissions, the Program Committee, with the help of external reviewers, selected 24 papers for presentation at the workshop. Each paper had at least three reviews and was extensively discussed in the comm- tee meeting. The papers were presented in 30-minute sessions at the workshop. One of the selected papers, while still included in the proceedings, was not p- sented because of an unfortunate visa problem that prevented the authors from attending the workshop. We werefortunateto havetwooutstanding keynoteaddressesatLCPC2006, both from UC Berkeley. Kathy Yelick presented ?Compilation Techniques for Partitioned Global Address Space Languages.? In this keynote she discussed the issues in developing programming models for large-scale parallel machines and clusters, and how PGAS languages compare to languages emerging from the DARPA HPCS program.She also presented compiler analysis and optimi- tion techniques developed in the context of UPC and Titanium source-to-source compilers for parallel program and communication optimizations. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4382 606 $aCompilers (Computer programs) 606 $aComputer programming 606 $aComputer science 606 $aComputer networks 606 $aComputer arithmetic and logic units 606 $aArtificial intelligence?Data processing 606 $aCompilers and Interpreters 606 $aProgramming Techniques 606 $aTheory of Computation 606 $aComputer Communication Networks 606 $aArithmetic and Logic Structures 606 $aData Science 615 0$aCompilers (Computer programs). 615 0$aComputer programming. 615 0$aComputer science. 615 0$aComputer networks. 615 0$aComputer arithmetic and logic units. 615 0$aArtificial intelligence?Data processing. 615 14$aCompilers and Interpreters. 615 24$aProgramming Techniques. 615 24$aTheory of Computation. 615 24$aComputer Communication Networks. 615 24$aArithmetic and Logic Structures. 615 24$aData Science. 676 $a005.453 702 $aAlmási$b Gheorghe$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aCascaval$b Calin$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aWu$b Peng$4edt$4http://id.loc.gov/vocabulary/relators/edt 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a996465976603316 996 $aLanguages and Compilers for Parallel Computing$9772572 997 $aUNISA