LEADER 03677nam 2200613 450 001 996465956103316 005 20211007114357.0 010 $a3-540-76650-2 024 7 $a10.1007/978-3-540-76650-6 035 $a(CKB)1000000000490578 035 $a(SSID)ssj0000317702 035 $a(PQKBManifestationID)11258694 035 $a(PQKBTitleCode)TC0000317702 035 $a(PQKBWorkID)10294841 035 $a(PQKB)10821892 035 $a(DE-He213)978-3-540-76650-6 035 $a(MiAaPQ)EBC3065436 035 $a(MiAaPQ)EBC6512619 035 $a(Au-PeEL)EBL6512619 035 $a(OCoLC)191471094 035 $a(PPN)123728940 035 $a(EXLCZ)991000000000490578 100 $a20211007d2007 uy 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt 182 $cc 183 $acr 200 00$aFormal methods and software engineering $e9th International Conference on Formal Engineering Methods, ICFEM 2007, Boca Raton, FL, USA, November 14-15, 2007 : proceedings /$fMichael Butler, Michael G. Hinchey, Maria M. Larrondo-Petrie (editors) 205 $a1st ed. 2007. 210 1$aBerlin :$cSpringer,$d[2007] 210 4$dİ2007 215 $a1 online resource (VIII, 387 p.) 225 1 $aProgramming and Software Engineering ;$v4789 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-76648-0 320 $aIncludes bibliographical references and index. 327 $aInvited Talks -- A System Development Process with Event-B and the Rodin Platform -- Challenges in Software Certification -- Security and Knowledge -- Integrating Formal Methods with System Management -- Formal Engineering of XACML Access Control Policies in VDM++ -- A Verification Framework for Agent Knowledge -- Embedded Systems -- From Model-Based Design to Formal Verification of Adaptive Embedded Systems -- Machine-Assisted Proof Support for Validation Beyond Simulink -- VeSTA: A Tool to Verify the Correct Integration of a Component in a Composite Timed System -- Testing -- Integrating Specification-Based Review and Testing for Detecting Errors in Programs -- Testing for Refinement in CSP -- Reducing Test Sequence Length Using Invertible Sequences -- Automated Analysis -- Model Checking with SAT-Based Characterization of ACTL Formulas -- Automating Refinement Checking in Probabilistic System Design -- Model Checking in Practice: Analysis of Generic Bootloader Using SPIN -- Model Checking Propositional Projection Temporal Logic Based on SPIN -- Hardware -- A Denotational Semantics for Handel-C Hardware Compilation -- Automatic Generation of Verified Concurrent Hardware -- Modeling and Verification of Master/Slave Clock Synchronization Using Hybrid Automata and Model-Checking -- Concurrency -- Efficient Symbolic Execution of Large Quantifications in a Process Algebra -- Formalizing SANE Virtual Processor in Thread Algebra -- Calculating and Composing Progress Properties in Terms of the Leads-to Relation -- Erratum -- Erratum to: Challenges in Software Certification. 410 0$aProgramming and Software Engineering ;$v4789 606 $aFormal methods (Computer science)$vCongresses 606 $aSoftware engineering$vCongresses 615 0$aFormal methods (Computer science) 615 0$aSoftware engineering 676 $a004.0151 702 $aHinchey$b Michael G$g(Michael Gerard),$f1969- 702 $aLarrondo-Petrie$b Mari?a M. 702 $aButler$b Michael$f1967- 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a996465956103316 996 $aFormal Methods and Software Engineering$9771999 997 $aUNISA