LEADER 07412nam 22008295 450 001 996465883203316 005 20230406001521.0 010 $a3-642-00641-8 024 7 $a10.1007/978-3-642-00641-8 035 $a(CKB)1000000000714674 035 $a(SSID)ssj0000319782 035 $a(PQKBManifestationID)11247500 035 $a(PQKBTitleCode)TC0000319782 035 $a(PQKBWorkID)10338642 035 $a(PQKB)11094227 035 $a(DE-He213)978-3-642-00641-8 035 $a(MiAaPQ)EBC3063997 035 $a(PPN)134126459 035 $a(EXLCZ)991000000000714674 100 $a20100301d2009 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aReconfigurable Computing: Architectures, Tools and Applications$b[electronic resource] $e5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009, Proceedings /$fedited by Jürgen Becker, Roger Woods, Peter Athanas, Fearghal Morgan 205 $a1st ed. 2009. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2009. 215 $a1 online resource (XV, 388 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v5453 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-642-00640-X 320 $aIncludes bibliographical references and index. 327 $aKeynotes -- FPGA Design Productivity ? A Discussion of the State of the Art and a Research Agenda -- Resiliency in Elemental Computing -- The Colour of Embedded Computation -- Applications 1 -- A HyperTransport 3 Physical Layer Interface for FPGAs -- Parametric Design for Reconfigurable Software-Defined Radio -- Applications 2 -- Hardware/Software FPGA Architecture for Robotics Applications -- Reconfigurable Operator Based Multimedia Embedded Processor -- FPGA Security and Bitstream Analysis -- A Protocol for Secure Remote Updates of FPGA Configurations -- FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing -- Fault Tolerant Systems -- An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications -- Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs -- Architectures -- A Novel Local Interconnect Architecture for Variable Grain Logic Cell -- Dynamically Adapted Low Power ASIPs -- Fast Optical Reconfiguration of a Nine-Context DORGA -- Place and Route Techniques -- Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep -- On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks -- A New Datapath Merging Method for Reconfigurable System -- Cryptography -- Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform -- Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm -- Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs -- Resource Allocation and Scheduling -- Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures -- Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems -- Applications 3 -- Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator -- FPGA-Based Anomalous Trajectory Detection Using SOFM -- Posters -- SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems -- A Parallel Branching Program Machine for Emulation of Sequential Circuits -- Memory Sharing Approach for TMR Softcore Processor -- The Need for Reconfigurable Routers in Networks-on-Chip -- Transparent Dynamic Reconfiguration as a Service of a System-Level Middleware -- Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder -- Tile-Based Fault Tolerant Approach Using Partial Reconfiguration -- Regular Expression Pattern Matching Supporting Constrained Repetitions -- Accelerating Calculations on the RASC Platform: A Case Study of the Exponential Function -- AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications -- CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers -- Object Tracking and Motion Capturing in Hardware-Accelerated Multi-camera System -- Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture -- A Hardware Accelerated Simulation Environment for Spiking Neural Networks -- Survey of Advanced CABAC Accelerator Architectures for Future Multimedia -- Real Time Simulation in Floating Point Precision Using FPGA Computing -- A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem -- A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems -- Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator -- ACCFS ? Operating System Integration of Computational Accelerators Using a VFS Approach -- A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. 330 $aThis book constitutes the refereed proceedings of the 5th International Workshop on Applied Reconfigurable Computing, ARC 2009, held in Karlsruhe, Germany, in March 2009. The 21 full papers and 21 short papers presented together with the abstracts of 3 keynote lectures were carefully reviewed and selected from about 100 submissions. The papers are organized in topical sections on FPGA security and bitstream analysis, fault tolerant systems, architectures, place and route techniques, cryptography, and resource allocation and scheduling, as well as on applications. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v5453 606 $aComputers 606 $aMicroprocessors 606 $aComputer architecture 606 $aComputer networks 606 $aElectronic digital computers?Evaluation 606 $aComputer systems 606 $aComputer vision 606 $aComputer Hardware 606 $aProcessor Architectures 606 $aComputer Communication Networks 606 $aSystem Performance and Evaluation 606 $aComputer System Implementation 606 $aComputer Vision 615 0$aComputers. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 0$aComputer networks. 615 0$aElectronic digital computers?Evaluation. 615 0$aComputer systems. 615 0$aComputer vision. 615 14$aComputer Hardware. 615 24$aProcessor Architectures. 615 24$aComputer Communication Networks. 615 24$aSystem Performance and Evaluation. 615 24$aComputer System Implementation. 615 24$aComputer Vision. 676 $a004 702 $aBecker$b Jürgen$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aWoods$b Roger$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aAthanas$b Peter$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aMorgan$b Fearghal$4edt$4http://id.loc.gov/vocabulary/relators/edt 712 12$aARC 2009 906 $aBOOK 912 $a996465883203316 996 $aReconfigurable Computing: Architectures, Tools and Applications$9772428 997 $aUNISA