LEADER 05774nam 22007815 450 001 996465848503316 005 20200704135558.0 024 7 $a10.1007/11556930 035 $a(CKB)1000000000213258 035 $a(SSID)ssj0000318342 035 $a(PQKBManifestationID)11231744 035 $a(PQKBTitleCode)TC0000318342 035 $a(PQKBWorkID)10310236 035 $a(PQKB)10560498 035 $a(DE-He213)978-3-540-32080-7 035 $a(MiAaPQ)EBC3068008 035 $a(PPN)123097649 035 $a(EXLCZ)991000000000213258 100 $a20100929d2005 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation$b[electronic resource] $e15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings /$fedited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest 205 $a1st ed. 2005. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2005. 215 $a1 online resource (XVI, 756 p.) 225 1 $aProgramming and Software Engineering ;$v3728 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$aPrinted edition: 9783540290131 320 $aIncludes bibliographical references and index. 327 $aSession 1: Low-Power Processors -- Session 2: Code Optimization for Low-Power -- Session 3: High-Level Design -- Session 4: Telecommunications and Signal Processing -- Session 5: Low-Power Circuits -- Session 6: System-on-Chip Design -- Session 7: Busses and Interconnections -- Session 8: Modeling -- Session 9: Design Automation -- Session 10: Low-Power Techniques -- Session 11: Memory and Register Files -- Poster Session 1: Applications -- Poster Session 2: Digital Circuits -- Poster Session 3: Analog and Physical Design -- Special Session: Digital Hearing Aids: Challenges and Solutions for Ultra Low Power -- Invited Talks. 330 $aWelcome to the proceedings of PATMOS 2005, the 15th in a series of international workshops.PATMOS2005wasorganizedbyIMECwithtechnicalco-sponsorshipfrom the IEEE Circuits and Systems Society. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the developmentof upcominggenerationsof integrated circuits and systems. The technical program of PATMOS 2005 contained state-of-the-art technical contri- tions, three invited talks, a special session on hearing-aid design, and an embedded - torial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, char- terization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert revi- ers, selected the 74 papers to be presented at PATMOS. The papers were divided into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were carried out per paper. Beyond the presentations of the papers, the PATMOS technical program was - riched by a series of speeches offered by world class experts, on important emerging research issues of industrial relevance. Prof. Jan Rabaey, Berkeley, USA, gave a talk on ?Traveling the Wild Frontier of Ulta Low-Power Design?, Dr. Sung Bae Park, S- sung, gave a presentation on ?DVL (Deep Low Voltage): Circuits and Devices?, Prof. 410 0$aProgramming and Software Engineering ;$v3728 606 $aLogic design 606 $aComputer software?Reusability 606 $aMicroprocessors 606 $aArithmetic and logic units, Computer 606 $aComputer-aided engineering 606 $aElectrical engineering 606 $aLogic Design$3https://scigraph.springernature.com/ontologies/product-market-codes/I12050 606 $aPerformance and Reliability$3https://scigraph.springernature.com/ontologies/product-market-codes/I12077 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 606 $aArithmetic and Logic Structures$3https://scigraph.springernature.com/ontologies/product-market-codes/I12026 606 $aComputer-Aided Engineering (CAD, CAE) and Design$3https://scigraph.springernature.com/ontologies/product-market-codes/I23044 606 $aElectrical Engineering$3https://scigraph.springernature.com/ontologies/product-market-codes/T24000 615 0$aLogic design. 615 0$aComputer software?Reusability. 615 0$aMicroprocessors. 615 0$aArithmetic and logic units, Computer. 615 0$aComputer-aided engineering. 615 0$aElectrical engineering. 615 14$aLogic Design. 615 24$aPerformance and Reliability. 615 24$aProcessor Architectures. 615 24$aArithmetic and Logic Structures. 615 24$aComputer-Aided Engineering (CAD, CAE) and Design. 615 24$aElectrical Engineering. 676 $a621.395 702 $aPaliouras$b Vassilis$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aVounckx$b Johan$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aVerkest$b Diederik$4edt$4http://id.loc.gov/vocabulary/relators/edt 712 02$aLINK (Online service) 906 $aBOOK 912 $a996465848503316 996 $aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation$9772134 997 $aUNISA