LEADER 05856nam 22008055 450 001 996465790003316 005 20200701161126.0 010 $a3-540-39724-8 024 7 $a10.1007/b93958 035 $a(CKB)1000000000212238 035 $a(SSID)ssj0000322361 035 $a(PQKBManifestationID)11234011 035 $a(PQKBTitleCode)TC0000322361 035 $a(PQKBWorkID)10282844 035 $a(PQKB)10094207 035 $a(DE-He213)978-3-540-39724-3 035 $a(MiAaPQ)EBC3088200 035 $a(PPN)155204432 035 $a(EXLCZ)991000000000212238 100 $a20121227d2003 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aCorrect Hardware Design and Verification Methods$b[electronic resource] $e12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings /$fedited by Daniel Geist, Enrico Tronci 205 $a1st ed. 2003. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2003. 215 $a1 online resource (XII, 432 p.) 225 1 $aLecture Notes in Computer Science,$x0302-9743 ;$v2860 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-20363-X 320 $aIncludes bibliographical references and index. 327 $aInvited Talks -- What Is beyond the RTL Horizon for Microprocessor and System Design? -- The Charme of Abstract Entities -- Tutorial -- The PSL/Sugar Specification Language A Language for all Seasons -- Software Verification -- Finding Regularity: Describing and Analysing Circuits That Are Not Quite Regular -- Predicate Abstraction with Minimum Predicates -- Efficient Symbolic Model Checking of Software Using Partial Disjunctive Partitioning -- Processor Verification -- Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP -- A Hazards-Based Correctness Statement for Pipelined Circuits -- Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT -- Automata Based Methods -- On Complementing Nondeterministic Büchi Automata -- Coverage Metrics for Formal Verification -- ?More Deterministic? vs. ?Smaller? Büchi Automata for Efficient LTL Model Checking -- Short Papers 1 -- An Optimized Symbolic Bounded Model Checking Engine -- Constrained Symbolic Simulation with Mathematica and ACL2 -- Semi-formal Verification of Memory Systems by Symbolic Simulation -- CTL May Be Ambiguous When Model Checking Moore Machines -- Specification Methods -- Reasoning about GSTE Assertion Graphs -- Towards Diagrammability and Efficiency in Event Sequence Languages -- Executing the Formal Semantics of the Accellera Property Specification Language by Mechanised Theorem Proving -- Protocol Verification -- On Combining Symmetry Reduction and Symbolic Representation for Efficient Model Checking -- On the Correctness of an Intrusion-Tolerant Group Communication Protocol -- Exact and Efficient Verification of Parameterized Cache Coherence Protocols -- Short Papers 2 -- Design and Implementation of an Abstract Interpreter for VHDL -- A Programming Language Based Analysis of Operand Forwarding -- Integrating RAM and Disk Based Verification within the Mur? Verifier -- Design and Verification of CoreConnectTM IP Using Esterel -- Theorem Proving -- Inductive Assertions and Operational Semantics -- A Compositional Theory of Refinement for Branching Time -- Linear and Nonlinear Arithmetic in ACL2 -- Bounded Model Checking -- Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking -- Convergence Testing in Term-Level Bounded Model Checking -- The ROBDD Size of Simple CNF Formulas -- Model Checking and Application -- Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems -- Finite Horizon Analysis of Markov Chains with the Mur? Verifier -- Improved Symbolic Verification Using Partitioning Techniques. 410 0$aLecture Notes in Computer Science,$x0302-9743 ;$v2860 606 $aComputers 606 $aComputer hardware 606 $aComputer logic 606 $aSoftware engineering 606 $aMathematical logic 606 $aArtificial intelligence 606 $aTheory of Computation$3https://scigraph.springernature.com/ontologies/product-market-codes/I16005 606 $aComputer Hardware$3https://scigraph.springernature.com/ontologies/product-market-codes/I1200X 606 $aLogics and Meanings of Programs$3https://scigraph.springernature.com/ontologies/product-market-codes/I1603X 606 $aSoftware Engineering$3https://scigraph.springernature.com/ontologies/product-market-codes/I14029 606 $aMathematical Logic and Formal Languages$3https://scigraph.springernature.com/ontologies/product-market-codes/I16048 606 $aArtificial Intelligence$3https://scigraph.springernature.com/ontologies/product-market-codes/I21000 615 0$aComputers. 615 0$aComputer hardware. 615 0$aComputer logic. 615 0$aSoftware engineering. 615 0$aMathematical logic. 615 0$aArtificial intelligence. 615 14$aTheory of Computation. 615 24$aComputer Hardware. 615 24$aLogics and Meanings of Programs. 615 24$aSoftware Engineering. 615 24$aMathematical Logic and Formal Languages. 615 24$aArtificial Intelligence. 676 $a621.395 702 $aGeist$b Daniel$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aTronci$b Enrico$4edt$4http://id.loc.gov/vocabulary/relators/edt 712 12$aCHARME 2003 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a996465790003316 996 $aCorrect Hardware Design and Verification Methods$9772373 997 $aUNISA