LEADER 06483nam 22008415 450 001 996465731103316 005 20230220170844.0 024 7 $a10.1007/11587514 035 $a(CKB)1000000000213527 035 $a(SSID)ssj0000318105 035 $a(PQKBManifestationID)11212484 035 $a(PQKBTitleCode)TC0000318105 035 $a(PQKBWorkID)10307794 035 $a(PQKB)11238344 035 $a(DE-He213)978-3-540-32272-6 035 $a(MiAaPQ)EBC3067851 035 $a(PPN)123098610 035 $a(EXLCZ)991000000000213527 100 $a20101222d2005 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aHigh Performance Embedded Architectures and Compilers$b[electronic resource] $eFirst International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings /$fedited by Tom Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer 205 $a1st ed. 2005. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2005. 215 $a1 online resource (XIV, 318 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v3793 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-32272-8 311 $a3-540-30317-0 320 $aIncludes bibliographical references and index. 327 $aInvited Program -- Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications -- Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges -- Software Defined Radio ? A High Performance Embedded Challenge -- I Analysis and Evaluation Techniques -- A Practical Method for Quickly Evaluating Program Optimizations -- Efficient Sampling Startup for Sampled Processor Simulation -- Enhancing Network Processor Simulation Speed with Statistical Input Sampling -- II Novel Memory and Interconnect Architectures -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation -- Streaming Sparse Matrix Compression/Decompression -- XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs -- III Security Architecture -- Memory-Centric Security Architecture -- A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management -- Arc3D: A 3D Obfuscation Architecture -- IV Novel Compiler and Runtime Techniques -- Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations -- Induction Variable Analysis with Delayed Abstractions -- Garbage Collection Hints -- V DomainSpecificArchitectures -- Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors -- Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture -- A Single (Unified) Shader GPU Microarchitecture for Embedded Systems -- A Low-Power DSP-Enhanced 32-Bit EISC Processor. 330 $aAs Chairmen of HiPEAC 2005, we have the pleasure of welcoming you to the proceedings of the ?rst international conference promoted by the HiPEAC N- work of Excellence. During the last year, HiPEAC has been building its clusters of researchers in computer architecture and advanced compiler techniques for embedded and high-performance computers. Recently, the Summer School has been the seed for a fruitful collaboration of renowned international faculty and young researchers from 23 countries with fresh new ideas. Now, the conference promises to be among the premier forums for discussion and debate on these research topics. Theprestigeofasymposiumismainlydeterminedbythequalityofitstech- cal program. This ?rst programlived up to our high expectations, thanks to the largenumber of strong submissions. The ProgramCommittee received a total of 84 submissions; only 17 were selected for presentation as full-length papers and another one as an invited paper. Each paper was rigorously reviewed by three ProgramCommittee members and at least one external referee. Many reviewers spent a great amount of e?ort to provide detailed feedback. In many cases, such feedback along with constructive shepherding resulted in dramatic improvement in the quality of accepted papers. The names of the Program Committee m- bers and the referees are listed in the proceedings. The net result of this team e?ort is that the symposium proceedings include outstanding contributions by authors from nine countries in three continents. In addition to paper presentations, this ?rst HiPEAC conference featured two keynotes delivered by prominent researchers from industry and academia. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v3793 606 $aComputer arithmetic and logic units 606 $aComputer systems 606 $aCompilers (Computer programs) 606 $aComputer input-output equipment 606 $aLogic design 606 $aMicroprocessors 606 $aComputer architecture 606 $aArithmetic and Logic Structures 606 $aComputer System Implementation 606 $aCompilers and Interpreters 606 $aInput/Output and Data Communications 606 $aLogic Design 606 $aProcessor Architectures 615 0$aComputer arithmetic and logic units. 615 0$aComputer systems. 615 0$aCompilers (Computer programs). 615 0$aComputer input-output equipment. 615 0$aLogic design. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 14$aArithmetic and Logic Structures. 615 24$aComputer System Implementation. 615 24$aCompilers and Interpreters. 615 24$aInput/Output and Data Communications. 615 24$aLogic Design. 615 24$aProcessor Architectures. 676 $a004 686 $a54.31$2bcl 702 $aConte$b Tom$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aNavarro$b Nacho$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aHwu$b Wen-mei W$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aValero$b Mateo$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aUngerer$b Theo$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a996465731103316 996 $aHigh Performance Embedded Architectures and Compilers$9772079 997 $aUNISA