LEADER 06702nam 22007455 450 001 996465658903316 005 20200705171258.0 010 $a3-540-68599-5 024 7 $a10.1007/3-540-61474-5 035 $a(CKB)1000000000234484 035 $a(SSID)ssj0000322081 035 $a(PQKBManifestationID)11246242 035 $a(PQKBTitleCode)TC0000322081 035 $a(PQKBWorkID)10281386 035 $a(PQKB)10865310 035 $a(DE-He213)978-3-540-68599-9 035 $a(PPN)155190822 035 $a(EXLCZ)991000000000234484 100 $a20121227d1996 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aComputer Aided Verification$b[electronic resource] $e8th International Conference, CAV '96, New Brunswick, NJ, USA, July 31 - August 3, 1996. Proceedings /$fedited by Rajeev Alur, Thomas Henzinger 205 $a1st ed. 1996. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d1996. 215 $a1 online resource (XIII, 479 p.) 225 1 $aLecture Notes in Computer Science,$x0302-9743 ;$v1102 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-61474-5 327 $aSymbolic verification of communication protocols with infinite state spaces using QDDs -- A conjunctively decomposed boolean representation for symbolic model checking -- Symbolic model checking using algebraic geometry -- A partition refinement algorithm for the ?-calculus -- Polynomial time algorithms for testing probabilistic bisimulation and simulation -- Pushdown processes: Games and model checking -- Module checking -- Automatic verification of parameterized synchronous systems -- HORNSAT, model checking, verification and games -- Verifying the SRT division algorithm using theorem proving techniques -- Modular verification of SRT division -- Mechanically verifying a family of multiplier circuits -- Verifying systems with replicated components in mur? -- Verification of arithmetic circuits by comparing two similar circuits -- Automated deduction and formal methods -- A platform for combining deductive with algorithmic verification -- Verifying invariants using theorem proving -- Deductive model checking -- Automated verification by induction with associative-commutative operators -- Analysis of timed systems based on time-abstracting bisimulations -- Verification of an Audio Protocol with bus collision using Uppaal -- Selective quantitative analysis and interval model checking: Verifying different facets of a system -- Verifying continuous time Markov chains -- Verifying safety properties of differential equations -- Temporal verification by diagram transformations -- Protocol verification by aggregation of distributed transactions -- Atomicity refinement and trace reduction theorems -- Powerful techniques for the automatic generation of invariants -- Saving space by fully exploiting invisible transitions -- Using on-the-fly verification techniques for the generation of test suites -- Automatic translation of natural language system specifications into temporal logic -- Verification of fair transition systems -- The state of Spin -- The Mur ? verification system -- The NCSU Concurrency Workbench -- The Concurrency Factory: A development environment for concurrent systems -- XVERSA: An integrated graphical and textual toolset for the specification and analysis of resource-bound real-time systems -- EVP: Integration of FDTs for the analysis and verification of communication protocols -- PVS: Combining specification, proof checking, and model checking -- STeP: Deductive-algorithmic verification of reactive and real-time systems -- Symbolic model checking -- COSPAN -- VIS: A system for verification and synthesis -- MDG tools for the verification of RTL designs -- CADP a protocol validation and verification toolbox -- The FC2TOOLS set -- The Real-Time Graphical Interval Logic toolset -- The METAFrame'95 environment -- Verification Support Environment -- Marrella: A tool for simulation and verification -- Verifying the safety of a practical concurrent garbage collector -- Verification by behaviour abstraction. 330 $aThis book constitutes the refereed proceedings of the 8th International Conference on Computer Aided Verification, CAV '96, held in New Brunswick, NJ, USA, in July/August 1996 as part of the FLoC '96 federated conference. The volume presents 32 revised full research contributions selected from a total of 93 submissions; also included are 20 carefully selected descriptions of tools and case studies. The set of papers reports the state-of-the-art of the theory and practice of computer assisted formal analysis methods for software and hardware systems; a certain emphasis is placed on verification tools and the algorithms and techniques that are needed for their implementation. 410 0$aLecture Notes in Computer Science,$x0302-9743 ;$v1102 606 $aComputer logic 606 $aComputers 606 $aComputer hardware 606 $aSoftware engineering 606 $aMathematical logic 606 $aSpecial purpose computers 606 $aLogics and Meanings of Programs$3https://scigraph.springernature.com/ontologies/product-market-codes/I1603X 606 $aTheory of Computation$3https://scigraph.springernature.com/ontologies/product-market-codes/I16005 606 $aComputer Hardware$3https://scigraph.springernature.com/ontologies/product-market-codes/I1200X 606 $aSoftware Engineering$3https://scigraph.springernature.com/ontologies/product-market-codes/I14029 606 $aMathematical Logic and Formal Languages$3https://scigraph.springernature.com/ontologies/product-market-codes/I16048 606 $aSpecial Purpose and Application-Based Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/I13030 615 0$aComputer logic. 615 0$aComputers. 615 0$aComputer hardware. 615 0$aSoftware engineering. 615 0$aMathematical logic. 615 0$aSpecial purpose computers. 615 14$aLogics and Meanings of Programs. 615 24$aTheory of Computation. 615 24$aComputer Hardware. 615 24$aSoftware Engineering. 615 24$aMathematical Logic and Formal Languages. 615 24$aSpecial Purpose and Application-Based Systems. 676 $a005.1015113 702 $aAlur$b Rajeev$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aHenzinger$b Thomas$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a996465658903316 996 $aComputer Aided Verification$9772228 997 $aUNISA