LEADER 06776nam 22007215 450 001 996465650903316 005 20210322192826.0 010 $a3-540-38394-8 024 7 $a10.1007/BFb0023712 035 $a(CKB)1000000000233700 035 $a(SSID)ssj0000322160 035 $a(PQKBManifestationID)11277525 035 $a(PQKBTitleCode)TC0000322160 035 $a(PQKBWorkID)10281491 035 $a(PQKB)10380562 035 $a(DE-He213)978-3-540-38394-9 035 $a(PPN)155201913 035 $a(EXLCZ)991000000000233700 100 $a20121227d1991 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aComputer-Aided Verification$b[electronic resource] $e2nd Internatonal Conference, CAV '90, New Brunswick, NJ, USA, June 18-21, 1990. Proceedings /$fedited by Edmund M. Clarke, Robert P. Kurshan 205 $a1st ed. 1991. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d1991. 215 $a1 online resource (XIV, 378 p.) 225 1 $aLecture Notes in Computer Science,$x0302-9743 ;$v531 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-54477-1 327 $aTemporal logic model checking: Two techniques for avoiding the state explosion problem -- Automatic verification of extensions of hardware descriptions -- Papetri : Environment for the analysis of PETRI nets -- Verifying temporal properties of sequential machines without building their state diagrams -- Formal verification of digital circuits using symbolic ternary system models -- Vectorized model checking for computation tree logic -- to a computational theory and implementation of sequential hardware equivalence -- Auto/autograph -- A data path verifier for register transfer level using temporal logic language Tokio -- The use of model checking in ATPG for sequential circuits -- Compositional design and verification of communication protocols, using labelled petri nets -- Issues arising in the analysis of L.0 -- Automated RTL verification based on predicate calculus -- On using protean to verify ISO FTAM protocol -- Quantitative temporal reasoning -- Using partial-order semantics to avoid the state explosion problem in asynchronous systems -- A stubborn attack on state explosion -- Using optimal simulations to reduce reachability graphs -- Using partial orders to improve automatic verification methods -- Compositional minimization of finite state systems -- Minimal model generation -- A context dependent equivalence relation between kripke structures -- The modular framework of computer-aided verification -- Verifying liveness properties by verifying safety properties -- Memory efficient algorithms for the verification of temporal properties -- A unified approach to the deadlock detection problem in networks of communicating finite state machines -- Branching time regular temporal logic for model checking with linear time complexity -- The algebraic feedback product of automata -- Synthesizing processes and schedulers from temporal specifications -- Task-driven supervisory control of discrete event systems -- A proof lattice-based technique for analyzing liveness of resource controllers -- Verification of a multiprocessor cache protocol using simulation relations and higher-order logic (summary) -- Computer assistance for program refinement -- Program verification by symbolic execution of hyperfinite ideal machines -- Extension of the Karp and miller procedure to lotos specifications -- An algebra for delay-insensitive circuits -- Finiteness conditions and structural construction of automata for all process algebras -- On automatically explaining bisimulation inequivalence. 330 $aThis volume contains the proceedings of the second workshop on Computer Aided Verification, held at DIMACS, Rutgers University, June 18-21, 1990. Itfeatures theoretical results that lead to new or more powerful verification methods. Among these are advances in the use of binary decision diagrams, dense time, reductions based upon partial order representations and proof-checking in controller verification. The motivation for holding a workshop on computer aided verification was to bring together work on effective algorithms or methodologies for formal verification - as distinguished, say,from attributes of logics or formal languages. The considerable interest generated by the first workshop, held in Grenoble, June 1989 (see LNCS 407), prompted this second meeting. The general focus of this volume is on the problem of making formal verification feasible for various models of computation. Specific emphasis is on models associated with distributed programs, protocols, and digital circuits. The general test of algorithm feasibility is to embed it into a verification tool, and exercise that tool on realistic examples: the workshop included sessionsfor the demonstration of new verification tools. 410 0$aLecture Notes in Computer Science,$x0302-9743 ;$v531 606 $aMathematical logic 606 $aComputers 606 $aComputer logic 606 $aSoftware engineering 606 $aSpecial purpose computers 606 $aMathematical Logic and Foundations$3https://scigraph.springernature.com/ontologies/product-market-codes/M24005 606 $aTheory of Computation$3https://scigraph.springernature.com/ontologies/product-market-codes/I16005 606 $aLogics and Meanings of Programs$3https://scigraph.springernature.com/ontologies/product-market-codes/I1603X 606 $aMathematical Logic and Formal Languages$3https://scigraph.springernature.com/ontologies/product-market-codes/I16048 606 $aSoftware Engineering$3https://scigraph.springernature.com/ontologies/product-market-codes/I14029 606 $aSpecial Purpose and Application-Based Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/I13030 615 0$aMathematical logic. 615 0$aComputers. 615 0$aComputer logic. 615 0$aSoftware engineering. 615 0$aSpecial purpose computers. 615 14$aMathematical Logic and Foundations. 615 24$aTheory of Computation. 615 24$aLogics and Meanings of Programs. 615 24$aMathematical Logic and Formal Languages. 615 24$aSoftware Engineering. 615 24$aSpecial Purpose and Application-Based Systems. 676 $a511.3 702 $aClarke$b Edmund M.$cJr.$g(Edmund Melson),$f1945-2020$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aKurshan$b Robert P$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a996465650903316 996 $aComputer Aided Verification$9772228 997 $aUNISA