LEADER 04152nam 22007095 450 001 996465621603316 005 20230329174917.0 010 $a3-642-36812-3 024 7 $a10.1007/978-3-642-36812-7 035 $a(CKB)3280000000007557 035 $a(DE-He213)978-3-642-36812-7 035 $a(SSID)ssj0000880061 035 $a(PQKBManifestationID)11495320 035 $a(PQKBTitleCode)TC0000880061 035 $a(PQKBWorkID)10872477 035 $a(PQKB)11290626 035 $a(MiAaPQ)EBC3093049 035 $a(PPN)169139662 035 $a(EXLCZ)993280000000007557 100 $a20130321d2013 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aReconfigurable Computing: Architectures, Tools and Applications$b[electronic resource] $e9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013, Proceedings /$fedited by Philip Brisk, José Gabriel de Figueiredo Coutinho, Pedro Diniz 205 $a1st ed. 2013. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2013. 215 $a1 online resource (XVI, 238 p. 104 illus.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v7806 300 $aInternational conference proceedings. 311 $a3-642-36811-5 320 $aIncludes bibliographical references and author index. 327 $aHeterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications -- Hardware Acceleration of Genetic Sequence Alignment -- An FPGA Acceleration for the Kd-tree Search in Photon Mapping -- SEU Resilience of DES, AES in SRAM-based FPGA -- An Architecture for IPv6 Lookup Using Parallel Index Generation Units -- Hardware Index to Set Partition Converter -- Teaching SoC Using Video Games to Improve Student Engagement -- Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-based Custom Computing -- Hardware Acceleration of Matrix Multiplication Over Small Prime Finite Fields -- Flexible Design of a Modular Simultaneous Exponentiation Core for Embedded Platforms -- Architecture for Transparent Binary Acceleration of Loops with Memory Accesses -- Parametric Optimization of Reconfigurable Designs using Machine Learning -- Fast Template-based Heterogeneous MPSoC Synthesis on FPGA -- Hierarchical and Multiple Switching NoC with Floorplan based Adaptability -- Performance Analysis And Optimization of High Density Tree-Based 3D Multilevel FPGA. 330 $aThis book constitutes the thoroughly refereed conference proceedings of the 9th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2013, held in Los Angeles, CA, USA, in March 2013. The 28 revised papers presented, consisting of 20 full papers and 11 poster papers were carefully selected from 41 submissions. The topics covered are applications, arithmetic, design optimization for FPGAs, architectures, place and routing. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v7806 606 $aComputers 606 $aComputer engineering 606 $aComputer networks 606 $aAlgorithms 606 $aComputer Hardware 606 $aComputer Engineering and Networks 606 $aAlgorithms 615 0$aComputers. 615 0$aComputer engineering. 615 0$aComputer networks. 615 0$aAlgorithms. 615 14$aComputer Hardware. 615 24$aComputer Engineering and Networks. 615 24$aAlgorithms. 676 $a006.3 702 $aBrisk$b Philip$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $ade Figueiredo Coutinho$b José Gabriel$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aDiniz$b Pedro$4edt$4http://id.loc.gov/vocabulary/relators/edt 712 12$aARC 2013 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a996465621603316 996 $aReconfigurable Computing: Architectures, Tools and Applications$9772428 997 $aUNISA