LEADER 06590nam 22008295 450 001 996465602203316 005 20230406065729.0 010 $a1-282-33186-8 010 $a9786612331862 010 $a3-642-03138-2 024 7 $a10.1007/978-3-642-03138-0 035 $a(CKB)1000000000761238 035 $a(EBL)450443 035 $a(OCoLC)437345750 035 $a(SSID)ssj0000294990 035 $a(PQKBManifestationID)11227336 035 $a(PQKBTitleCode)TC0000294990 035 $a(PQKBWorkID)10312698 035 $a(PQKB)11360098 035 $a(DE-He213)978-3-642-03138-0 035 $a(MiAaPQ)EBC450443 035 $a(MiAaPQ)EBC6416137 035 $a(PPN)136310788 035 $a(EXLCZ)991000000000761238 100 $a20100301d2009 u| 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aEmbedded Computer Systems: Architectures, Modeling, and Simulation$b[electronic resource] $e9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009, Proceedings /$fedited by Koen Bertels, Nikitas Dimopoulos, Cristina Silvano, Stephan Wong 205 $a1st ed. 2009. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2009. 215 $a1 online resource (354 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v5657 300 $aDescription based upon print version of record. 311 $a3-642-03137-4 320 $aIncludes bibliographical references and index. 327 $aBeachnote -- What Else Is Broken? Can We Fix It? -- Architectures for Multimedia -- Programmable and Scalable Architecture for Graphics Processing Units -- The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors -- CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey -- Programmable Accelerators for Reconfigurable Video Decoder -- Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study -- Multiple Description Scalable Coding for Video Transmission over Unreliable Networks -- Multi/Many Cores Architectures -- Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC -- Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture -- Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management -- A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA -- VLSI Architectures Design -- Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing -- Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata -- Prediction in Dynamic SDRAM Controller Policies -- Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI -- Architecture Modeling and Exploration Tools -- Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration -- Modeling Scalable SIMD DSPs in LISA -- NoGAP: A Micro Architecture Construction Framework -- A Comparison of NoTA and GENESYS -- Special Session 1: Instruction-Set Customization -- to Instruction-Set Customization -- Constraint-Driven Identification of Application Specific Instructions in the DURASE System -- A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs) -- Runtime Adaptive Extensible Embedded Processors ? A Survey -- Special Session 2: The Future of Reconfigurable Computing and Processor Architectures -- to the Future of Reconfigurable Computing and Processor Architectures -- An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems -- Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study -- Reconfigurable Multicore Server Processors for Low Power Operation -- Reconfigurable Computing in the New Age of Parallelism -- Reconfigurable Multithreading Architectures: A Survey -- Special Session 3: Mastering Cell BE and GPU Execution Platforms -- to Mastering Cell BE and GPU Execution Platforms -- Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors -- Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs -- Experiences with Cell-BE and GPU for Tomography -- Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell -- Exploiting Locality on the Cell/B.E. through Bypassing -- Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System. 330 $aThis book constitutes the refereed proceedings of the 9th International Workshop on Architectures, Modeling, and Simulation, SAMOS 2009, held on Samos, Greece, on July 20-23, 2009. The 18 regular papers presented were carefully reviewed and selected from 52 submissions. The papers are organized in topical sections on architectures for multimedia, multi/many cores architectures, VLSI architectures design, architecture modeling and exploration tools. In addition there are 14 papers from three special sessions which were organized on topics of current interest: instruction-set customization, reconfigurable computing and processor architectures, and mastering cell BE and GPU execution platforms. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v5657 606 $aComputer systems 606 $aComputers 606 $aMicroprocessors 606 $aComputer architecture 606 $aComputer networks 606 $aElectronic digital computers?Evaluation 606 $aComputer System Implementation 606 $aComputer Hardware 606 $aProcessor Architectures 606 $aComputer Communication Networks 606 $aSystem Performance and Evaluation 615 0$aComputer systems. 615 0$aComputers. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 0$aComputer networks. 615 0$aElectronic digital computers?Evaluation. 615 14$aComputer System Implementation. 615 24$aComputer Hardware. 615 24$aProcessor Architectures. 615 24$aComputer Communication Networks. 615 24$aSystem Performance and Evaluation. 676 $a004.22 702 $aBertels$b Koen 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bUtOrBLW 906 $aBOOK 912 $a996465602203316 996 $aEmbedded Computer Systems: Architectures, Modeling, and Simulation$9772127 997 $aUNISA