LEADER 01441nam0-2200469---450- 001 990000085900203316 005 20060920102134.0 010 $a92-871-2991-6 035 $a0008590 035 $aUSA010008590 035 $a(ALEPH)000008590USA01 035 $a0008590 100 $a20000914d1996----|||y0itay0103----ba 101 0 $aeng 102 $aFR 105 $a||||||||001yy 200 1 $aEuropean pharmacopoeia$epublished in accordance with the convention on the elaboration of a European pharmacopoeia (European treaty series No.50) 205 $a3. ed. 210 $aStrasbourg$cCouncil of Europe$dcopyr. 1996 215 $aXVIII, 1799 p.$d30 cm 606 0 $aFarmacopea$yEuropa 676 $a615.11 801 $aIT$bSALBC$gISBD 912 $a990000085900203316 951 $a615.11 EUR$b2204 Farm.$c615.11$d00002553 959 $aBK 969 $aFAR 979 $c20000914$lUSA01$h1739 979 $c20001019$lUSA01$h1056 979 $c20001019$lUSA01$h1454 979 $c20001019$lUSA01$h1501 979 $c20001019$lUSA01$h1539 979 $c20001024$lUSA01$h1515 979 $c20001027$lUSA01$h1519 979 $c20001027$lUSA01$h1523 979 $c20001110$lUSA01$h1710 979 $c20001124$lUSA01$h1208 979 $c20020403$lUSA01$h1616 979 $aPATRY$b90$c20040406$lUSA01$h1607 979 $aPATRY$b90$c20060920$lUSA01$h1021 996 $aEuropean pharmacopoeia$9724240 997 $aUNISA LEADER 06212nam 22008655 450 001 996465510303316 005 20230312192111.0 010 $a1-280-38556-1 010 $a9786613563484 010 $a3-642-11515-2 024 7 $a10.1007/978-3-642-11515-8 035 $a(CKB)2670000000003390 035 $a(SSID)ssj0000399487 035 $a(PQKBManifestationID)11279226 035 $a(PQKBTitleCode)TC0000399487 035 $a(PQKBWorkID)10376499 035 $a(PQKB)11610456 035 $a(DE-He213)978-3-642-11515-8 035 $a(MiAaPQ)EBC3064980 035 $a(PPN)149057075 035 $a(EXLCZ)992670000000003390 100 $a20100301d2010 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aHigh Performance Embedded Architectures and Compilers$b[electronic resource] $e5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings /$fedited by Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell 205 $a1st ed. 2010. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2010. 215 $a1 online resource (XIII, 370 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v5952 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-642-11514-4 320 $aIncludes bibliographical references and index. 327 $aInvited Program -- Embedded Systems as Datacenters -- Larrabee: A Many-Core Intel Architecture for Visual Computing -- Architectural Support for Concurrency -- Remote Store Programming -- Low-Overhead, High-Speed Multi-core Barrier Synchronization -- Improving Performance by Reducing Aborts in Hardware Transactional Memory -- Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems -- Compilation and Runtime Systems -- Split Register Allocation: Linear Complexity Without the Performance Penalty -- Trace-Based Data Layout Optimizations for Multi-core Processors -- Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors -- Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures -- Reconfigurable and Customized Architectures -- Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions -- Accelerating XML Query Matching through Custom Stack Generation on FPGAs -- An Application-Aware Load Balancing Strategy for Network Processors -- Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays -- Multicore Efficiency, Reliability, and Power -- Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors -- Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors -- RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor -- Performance and Power Aware CMP Thread Allocation Modeling -- Memory Organization and Optimization -- Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching -- Scalable Shared-Cache Management by Containing Thrashing Workloads -- SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs -- DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems -- Programming and Analysis of Accelerators -- Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor -- Analysis of Task Offloading for Accelerators -- Offload ? Automating Code Migration to Heterogeneous Multicore Systems -- Computer Generation of Efficient Software Viterbi Decoders. 330 $aThis book constitutes the refereed proceedings of the 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, held in Pisa, Italy, in January 2010. The 23 revised full papers presented together with the abstracts of 2 invited keynote addresses were carefully reviewed and selected from 94 submissions. The papers are organized in topical sections on architectural support for concurrency; compilation and runtime systems; reconfigurable and customized architectures; multicore efficiency, reliability, and power; memory organization and optimization; and programming and analysis of accelerators. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v5952 606 $aComputer programming 606 $aComputer arithmetic and logic units 606 $aMicroprocessors 606 $aComputer architecture 606 $aComputer input-output equipment 606 $aLogic design 606 $aComputer networks 606 $aProgramming Techniques 606 $aArithmetic and Logic Structures 606 $aProcessor Architectures 606 $aInput/Output and Data Communications 606 $aLogic Design 606 $aComputer Communication Networks 615 0$aComputer programming. 615 0$aComputer arithmetic and logic units. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 0$aComputer input-output equipment. 615 0$aLogic design. 615 0$aComputer networks. 615 14$aProgramming Techniques. 615 24$aArithmetic and Logic Structures. 615 24$aProcessor Architectures. 615 24$aInput/Output and Data Communications. 615 24$aLogic Design. 615 24$aComputer Communication Networks. 676 $a005.4/53 702 $aPatt$b Yale N$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aFoglia$b Pierfrancesco$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aDuesterwald$b Evelyn$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aFaraboschi$b Paolo$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aMartorell$b Xavier$4edt$4http://id.loc.gov/vocabulary/relators/edt 712 12$aHiPEAC 2010 906 $aBOOK 912 $a996465510303316 996 $aHigh Performance Embedded Architectures and Compilers$9772079 997 $aUNISA