LEADER 06356nam 22007575 450 001 996465337203316 005 20200701111742.0 010 $a3-540-46183-3 024 7 $a10.1007/3-540-51284-5 035 $a(CKB)1000000000233401 035 $a(SSID)ssj0000325542 035 $a(PQKBManifestationID)11254102 035 $a(PQKBTitleCode)TC0000325542 035 $a(PQKBWorkID)10325425 035 $a(PQKB)10461792 035 $a(DE-He213)978-3-540-46183-8 035 $a(PPN)155219790 035 $a(EXLCZ)991000000000233401 100 $a20121227d1989 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aPARLE '89 - Parallel Architectures and Languages Europe$b[electronic resource] $eVolume I: Parallel Architectures, Eindhoven, The Netherlands, June 12-16, 1989; Proceedings /$fedited by Eddy Odijk, Martin Rem, Jean-Claude Syre 205 $a1st ed. 1989. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d1989. 215 $a1 online resource (XIII, 479 p.) 225 1 $aLecture Notes in Computer Science,$x0302-9743 ;$v365 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-51284-5 327 $aThe cache coherence protocol of the Data Diffusion Machine -- Universal mechanisms for concurrency -- Serial multiport memory multiprocessors -- Modeling and analysis of multiprocessor systems with priority and multiple resources allocation to the tasks -- Achieving low cost synchronization in a multiprocessor system -- The Synchronous Dataflow MAchine: Architecture and performance -- The lady programming environment for distributed operating systems -- A static scheduling system for a parallel machine (SM)2-II -- Distributed implementation of programmed graph reduction -- Parallel object-oriented descriptions of graph reduction machines -- MaRS, a combinator graph reduction multiprocessor -- High-performance parallel graph reduction -- An efficient distributed garbage collection algorithm -- Mark DURING sweep rather than mark THEN sweep -- Architecture of a communication network processor -- The feasibility of a general-purpose parallel computer using WSI -- A coarse grain parallel architecture for functional languages -- A Functional Programming environment supporting execution, partial execution and transformation -- The gene concept and its implementation for a dataflow schemed parallel computer -- Hybrid structure: A scheme for handling data structures in a data flow environment -- Implementation conditions for delay insensitive circuits -- POOL and DOOM a survey of esprit 415 subproject A, Philips research laboratories -- Multi-level simulator for VLSI on the parallel object-oriented machine -- Overview of a parallel reduction machine project II -- A parallel database accelerator -- IDEAL & K-LEAF implementation: a progress report -- The sto//mann data flow machine -- Partheo: A parallel inference machine ESPRIT 415 subproject F. 330 $aSince the first PARLE conference, PARLE '87, attracted more than 300 participants, it was considered a useful and successful forum and encouraged the organization of this second issue known as PARLE '89. The initiative for these conferences was taken by project 415 of ESPRIT (the European Strategic Programme for Research and Development in Information Technology of the Commission of the European Communities). Their scope covers central themes in the area of parallel architectures and languages, including such topics as concurrent, object-oriented, logic and functional programming; MIMD, dataflow, inference and reduction machines; design and verification of parallel systems; VLSI, WSI and RISC architectures; performance evaluation, memory management, systolic arrays, applications and special purpose architectures. The five invited lectures present the state of the art and advanced developments in major research areas related to the topics of the conference. Of the more than 150 submitted papers, 45 were selected for presentation. Furthermore the program of PARLE '89 comprises presentations on the subprojects which together constitute ESPRIT project 415. Parallel architectures based on a variety of programming styles (object-oriented, logic, functional, dataflow) are represented in these overviews. 410 0$aLecture Notes in Computer Science,$x0302-9743 ;$v365 606 $aArchitecture, Computer 606 $aMicroprocessors 606 $aComputer communication systems 606 $aSpecial purpose computers 606 $aComputer system failures 606 $aComputer programming 606 $aComputer System Implementation$3https://scigraph.springernature.com/ontologies/product-market-codes/I13057 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 606 $aComputer Communication Networks$3https://scigraph.springernature.com/ontologies/product-market-codes/I13022 606 $aSpecial Purpose and Application-Based Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/I13030 606 $aSystem Performance and Evaluation$3https://scigraph.springernature.com/ontologies/product-market-codes/I13049 606 $aProgramming Techniques$3https://scigraph.springernature.com/ontologies/product-market-codes/I14010 615 0$aArchitecture, Computer. 615 0$aMicroprocessors. 615 0$aComputer communication systems. 615 0$aSpecial purpose computers. 615 0$aComputer system failures. 615 0$aComputer programming. 615 14$aComputer System Implementation. 615 24$aProcessor Architectures. 615 24$aComputer Communication Networks. 615 24$aSpecial Purpose and Application-Based Systems. 615 24$aSystem Performance and Evaluation. 615 24$aProgramming Techniques. 676 $a003.3 702 $aOdijk$b Eddy$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aRem$b Martin$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aSyre$b Jean-Claude$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a996465337203316 996 $aPARLE '89 - Parallel Architectures and Languages Europe$92831533 997 $aUNISA