LEADER 05699nam 22008535 450 001 996465311503316 005 20200630081819.0 010 $a3-540-30205-0 024 7 $a10.1007/b100662 035 $a(CKB)1000000000212563 035 $a(SSID)ssj0000180258 035 $a(PQKBManifestationID)11167522 035 $a(PQKBTitleCode)TC0000180258 035 $a(PQKBWorkID)10149118 035 $a(PQKB)10263566 035 $a(DE-He213)978-3-540-30205-6 035 $a(MiAaPQ)EBC3087718 035 $a(PPN)155233351 035 $a(EXLCZ)991000000000212563 100 $a20121227d2004 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aIntegrated Circuit and System Design$b[electronic resource] $ePower and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings /$fedited by Enrico Macii, Vassilis Paliouras, Odysseas Koufopavlou 205 $a1st ed. 2004. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2004. 215 $a1 online resource (XVI, 916 p.) 225 1 $aLecture Notes in Computer Science,$x0302-9743 ;$v3254 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-23095-5 320 $aIncludes bibliographical references at the end of each chapters and index. 327 $aKeynote Speech -- Invited Talks -- Embedded Tutorials -- Session 1: Buses and Communication -- Session 2: Circuits and Devices (I) -- Session 3: Low Power (I) -- Session 4: Architectures -- Session 5: Asynchronous Circuits -- Session 6: System Design -- Session 7: Circuits and Devices (II) -- Session 8: Interconnect and Physical Design -- Session 9: Security and Safety -- Session 10: Low Power (II) -- Session 11: Low-Power Processing (Poster) -- Session 12: Digital Design (Poster) -- Session 13: Modeling and Simulation (Poster). 330 $aWelcometotheproceedingsofPATMOS2004,thefourteenthinaseriesofint- national workshops. PATMOS 2004 was organized by the University of Patras with technical co-sponsorship from the IEEE Circuits and Systems Society. Over the years, the PATMOS meeting has evolved into an important - ropean event, where industry and academia meet to discuss power and timing aspects in modern integrated circuit and system design. PATMOS provides a forum for researchers to discuss and investigate the emerging challenges in - sign methodologies and tools required to develop the upcoming generations of integrated circuits and systems. We realized this vision this year by providing a technical program that contained state-of-the-art technical contributions, a keynote speech, three invited talks and two embedded tutorials. The technical program focused on timing, performance and power consumption, as well as architectural aspects, with particular emphasis on modelling, design, charac- rization, analysis and optimization in the nanometer era. This year a record 152 contributions were received to be considered for p- sible presentation at PATMOS. Despite the choice for an intense three-day m- ting, only 51 lecture papers and 34 poster papers could be accommodated in the single-track technical program. The Technical Program Committee, with the - sistance of additional expert reviewers, selected the 85 papers to be presented at PATMOS and organized them into 13 technical sessions. As was the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were received per manuscript. 410 0$aLecture Notes in Computer Science,$x0302-9743 ;$v3254 606 $aElectronics 606 $aMicroelectronics 606 $aComputers 606 $aLogic design 606 $aComputer software?Reusability 606 $aMicroprocessors 606 $aArithmetic and logic units, Computer 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 606 $aTheory of Computation$3https://scigraph.springernature.com/ontologies/product-market-codes/I16005 606 $aLogic Design$3https://scigraph.springernature.com/ontologies/product-market-codes/I12050 606 $aPerformance and Reliability$3https://scigraph.springernature.com/ontologies/product-market-codes/I12077 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 606 $aArithmetic and Logic Structures$3https://scigraph.springernature.com/ontologies/product-market-codes/I12026 615 0$aElectronics. 615 0$aMicroelectronics. 615 0$aComputers. 615 0$aLogic design. 615 0$aComputer software?Reusability. 615 0$aMicroprocessors. 615 0$aArithmetic and logic units, Computer. 615 14$aElectronics and Microelectronics, Instrumentation. 615 24$aTheory of Computation. 615 24$aLogic Design. 615 24$aPerformance and Reliability. 615 24$aProcessor Architectures. 615 24$aArithmetic and Logic Structures. 676 $a621.3815 702 $aMacii$b Enrico$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aPaliouras$b Vassilis$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aKoufopavlou$b Odysseas$4edt$4http://id.loc.gov/vocabulary/relators/edt 712 02$aPanepiste?mio Patro?n. 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a996465311503316 996 $aIntegrated Circuit and System Design$9772327 997 $aUNISA