LEADER 07307nam 2200493 450 001 996464419403316 005 20220513112749.0 010 $a3-030-79701-5 035 $a(CKB)5590000000549930 035 $a(MiAaPQ)EBC6711405 035 $a(Au-PeEL)EBL6711405 035 $a(OCoLC)1265345504 035 $a(PPN)257357149 035 $a(EXLCZ)995590000000549930 100 $a20220513d2021 uy 0 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aSelf aware security for real time task schedules in reconfigurable hardware platforms /$fKrishnendu Guha, Sangeet Saha, Amlan Chakrabarti 210 1$aCham, Switzerland :$cSpringer,$d[2021] 210 4$d©2021 215 $a1 online resource (195 pages) 311 $a3-030-79700-7 327 $aIntro -- Preface -- Acknowledgements -- Contents -- About the Authors -- Part I Introduction -- 1 Introduction -- 1.1 Introduction -- 1.2 Real-Time Systems -- 1.2.1 Hard Versus Soft Real-Time -- 1.2.2 Important Features of Real-Time Systems -- 1.2.3 Real-Time Tasks and Its Classifications -- 1.3 Field Programmable Gate Arrays (FPGAs)-Its Evolution and Conceptual Background -- 1.3.1 Introduction to FPGAs -- 1.3.2 FPGA Technology: Evolution of Its Conceptual Path -- 1.3.3 FPGA Architectures -- 1.3.4 Heterogeneous FPGAs -- 1.3.5 Closer Look into CLBs -- 1.3.6 FPGA Design Flow -- 1.3.7 Processors Within Re-configurable Targets -- 1.3.8 Dynamic and Partial Reconfiguration -- 1.3.9 Real-Time Hardware Tasks -- 1.3.10 Spatio-temporal Management of Hardware Tasks -- 1.3.11 Various Task Placement Strategies for FPGAs -- 1.3.12 Fragmentations Control Based Placement Strategies -- 1.4 Conclusions -- References -- Part II Scheduling -- 2 Real-Time Scheduling: Background and Trends -- 2.1 Introduction -- 2.2 A Background on Scheduling -- 2.2.1 Resource Constraint -- 2.2.2 Metrics for Scheduling Evaluation -- 2.3 Real-Time Scheduling -- 2.3.1 Offline Versus Online Scheduling -- 2.3.2 Real-Time Scheduling for Uniprocessor Systems -- 2.3.3 Processor Utilization -- 2.3.4 Real-Time Scheduling for Multiprocessor Systems -- 2.4 Fault Tolerance for Real-Time Scheduling -- 2.4.1 Fault Types -- 2.4.2 Fault Detection -- 2.4.3 Fault Tolerance Techniques -- 2.4.4 Fault Tolerance Scheduling -- 2.5 Imprecise Computation Based Real-Time Task -- 2.6 Real-Time Scheduling on FPGA -- 2.6.1 Challenges for FPGA-Based Scheduling -- 2.6.2 Preemption of Hardware Tasks -- 2.6.3 Existing FPGA-based Real-Time Scheduling Techniques -- 2.6.4 Real-Time Preemptive Scheduling: Uniprocessors Versus Multiprocessors Versus FPGAs -- 2.7 Conclusions -- References. 327 $a3 Scheduling Algorithms for Reconfigurable Systems -- 3.1 Introduction -- 3.2 Challenge for Devising Real-Time Scheduling Algorithm for FPGAs -- 3.3 System Model and Assumptions -- 3.4 Scheduling Strategies -- 3.4.1 Scheduling Algorithm for Full Reconfigurable Systems -- 3.4.2 Scheduling Algorithm for Partially Reconfigurable Systems -- 3.4.3 Handling Dynamic Tasks -- 3.4.4 For Fully Reconfigurable FPGAs -- 3.4.5 For Runtime Partially Reconfigurable Systems -- 3.5 Experiments and Results -- 3.5.1 Results and Analysis -- 3.6 Hardware Prototype for Multiple Tasks Processing on FPGA -- 3.7 Conclusion -- References -- Part III Security -- 4 Introduction to Hardware Security for FPGA Based Systems -- 4.1 Introduction -- 4.2 Overview of Hardware Threats -- 4.2.1 Hardware Trojan Horses (HTHs) -- 4.2.2 Piracy and Overbuilding -- 4.2.3 Reverse Engineering -- 4.2.4 Counterfeiting -- 4.3 Hardware Trust and Hardware Security -- 4.3.1 Hardware Trust -- 4.3.2 Hardware Security -- 4.4 Life Cycle of FPGA Based System -- 4.4.1 Consumers -- 4.4.2 FPGA Based System Developer -- 4.4.3 Contract Manufacturer -- 4.4.4 FPGA Vendor -- 4.4.5 Off-Shore Foundry -- 4.4.6 Off-Shore Facility -- 4.4.7 Third Party Reconfigurable IP/Bitstream Developers -- 4.4.8 Value Added Reseller (VAR) -- 4.5 Overview of Threats Related to FPGA Based Systems -- 4.5.1 Attacks Related to Bitstreams -- 4.5.2 Attacks Related to FPGAs -- 4.6 Overview of Hardware Security Techniques for FPGA Based Systems -- 4.6.1 Test Time Detection Techniques -- 4.6.2 Protection via Authentication -- 4.6.3 Runtime Mitigation Mechanisms -- 4.7 Present Scope -- 4.8 Conclusion -- References -- 5 Bypassing Passive Attacks -- 5.1 Introduction -- 5.2 System Model -- 5.2.1 Fully Re-configurable Mode -- 5.2.2 Partially Re-configurable Mode -- 5.3 Threat Model -- 5.3.1 Vulnerability Present in Bitstreams. 327 $a5.3.2 Vulnerability in FPGA Device -- 5.4 Self Aware Security to Bypass Passive Threats -- 5.4.1 Existing Strategies and Limitations -- 5.4.2 Security Mechanism -- 5.4.3 Working of Self Aware Agent (SAA) -- 5.4.4 Algorithm and Explanation of Proposed Mechanism -- 5.4.5 Demonstration -- 5.5 Experimentation and Results -- 5.5.1 Experimentation -- 5.5.2 Result Analysis -- 5.6 Conclusion -- References -- 6 Counteracting Active Attacks -- 6.1 Introduction -- 6.2 System Model -- 6.2.1 Single FPGA Based System -- 6.2.2 Multi FPGA Based System -- 6.3 Threat Scenario -- 6.3.1 Vulnerability in RIPs/Bitstreams -- 6.3.2 Vulnerability in FPGAs -- 6.4 Redundancy Based Mechanism and Application to Current Context -- 6.4.1 Application for Single FPGA Based Platform -- 6.4.2 Application for Multi FPGA Based Platform -- 6.5 Self Aware Mechanism -- 6.5.1 Offline Phase -- 6.5.2 Online Phase -- 6.5.3 Handling Non-periodic Tasks -- 6.5.4 Fault Handling -- 6.5.5 Demonstration -- 6.6 Experimentation and Results -- 6.6.1 Experimentation -- 6.6.2 Result Analysis -- 6.7 Conclusion -- References -- 7 Handling Power Draining Attacks -- 7.1 Introduction -- 7.2 System Model -- 7.2.1 Working of System Components -- 7.2.2 Nature of Tasks -- 7.3 Threat Model -- 7.3.1 Illustrative Example -- 7.4 Limitations of Existing Techniques -- 7.5 Self Aware Strategy to Handle Power Draining Attacks -- 7.5.1 Periodic Task Handling -- 7.5.2 Determination of Reference Power Dissipation Values of Schedules -- 7.5.3 Mechanism for Detection of Affected Resources -- 7.5.4 Action on Detection of Vulnerability -- 7.5.5 Handling of Non-periodic Tasks -- 7.6 Experimentation and Result Analysis -- 7.6.1 Experimentation -- 7.6.2 Result Analysis for Periodic Tasks -- 7.6.3 Result Analysis for Non-periodic Tasks -- 7.7 Conclusion -- References. 327 $aCorrection to: Scheduling Algorithms for Reconfigurable Systems -- Correction to: Chapter 3 in: K. Guha et al., Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms, https://doi.org/10.1007/978-3-030-79701-03. 606 $aEmbedded computer systems$xSecurity measures 606 $aAdaptive computing systems$xSecurity measures 615 0$aEmbedded computer systems$xSecurity measures. 615 0$aAdaptive computing systems$xSecurity measures. 676 $a006.22 700 $aGuha$b Krishnendu$01069171 702 $aSaha$b Sangeet 702 $aChakrabarti$b Amlan 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a996464419403316 996 $aSelf aware security for real time task schedules in reconfigurable hardware platforms$92843068 997 $aUNISA LEADER 01089cam0-2200337---450 001 990008684450403321 005 20230511083350.0 010 $a84-8155-789-7 010 $a846072560X 035 $a000868445 035 $aFED01000868445 035 $a(Aleph)000868445FED01 100 $a20080704d2001----km-y0itay50------ba 101 0 $aspa 102 $aES 105 $aa-------001yy 200 1 $a<>comercio, los negocios y las finanzas en el mundo romano$fManuel J. García Garrido 210 $aMadrid$cFundación de Estudios Romanos$cEditorial Dykinson$d2001 215 $a177 p.$cill.$d25 cm 320 $aBibliogr.: p. 140-160 700 1$aGarcía Garrido,$bManuel J.$g$0412806 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990008684450403321 952 $aFONDO PROFESSOR ANTONIO GUARINO IV M 32$bG/421$fFGBC 952 $aXIX A 107$b279$fNAP02 952 $aXIX A 107 (al. es.)$b2719$fNAP02 959 $aFGBC 959 $aNAP02 996 $aComercio, los negocios y las finanzas en el mundo romano$9717346 997 $aUNINA