LEADER 05386nam 22006975 450 001 996418307303316 005 20230330000032.0 010 $a3-030-52794-8 024 7 $a10.1007/978-3-030-52794-5 035 $a(CKB)4100000011343260 035 $a(DE-He213)978-3-030-52794-5 035 $a(MiAaPQ)EBC6273248 035 $a(PPN)254922619 035 $a(EXLCZ)994100000011343260 100 $a20200708d2020 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aArchitecture of Computing Systems ? ARCS 2020$b[electronic resource] $e33rd International Conference, Aachen, Germany, May 25?28, 2020, Proceedings /$fedited by André Brinkmann, Wolfgang Karl, Stefan Lankes, Sven Tomforde, Thilo Pionteck, Carsten Trinitis 205 $a1st ed. 2020. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2020. 215 $a1 online resource (XII, 257 p. 112 illus., 62 illus. in color.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v12155 311 $a3-030-52793-X 327 $aMain Conference -- Approximate Data Dependence Pro ling based on Abstract Interval and Congruent Domains -- Evaluating Dynamic Task Scheduling with Priorities and Adaptive Aging in a Task-based Runtime System -- An Architecture for Solving the Eigenvalue Problem on Embedded FPGAs -- ECC Memory for Fault Tolerant RISC-V Processors -- 3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs -- Towards a Priority-Based Task Distribution Strategy for an Artificial Hormone System -- He..ro DB: A Concept for Parallel Data Processing on Heterogeneous Hardware -- Investigating Transactional Memory for High Performance Embedded Systems -- X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-based MPSoCs -- Engineering an Optimized Instruction Set Architecture for AMIDAR Processors -- Scaling Logic Locking Schemes to Multi-Module Hardware Designs -- Exploration of Power Domain Partitioning with Concurrent Task Mapping and Scheduling for Application-specific Multi-core SoCs -- FORMUS3IC Workshop -- Scalable, Decentralized Battery Management System Based on Self-Organizing Nodes -- Security Improvements by Separating the Cryptographic Protocol from the Network Stack onto a Multi-MCU Architecture -- Equally Distributed Bus-Communication Access Rights for Inter MCU Communication using Multimaster SPI -- Workshop on Computer Architectures in Space (CompSpace) -- On the Evaluation of SEU Effects on AXI Interconnect within AP-SoCs -- Satellite Onboard Data Reduction using a Risc-V core inside an RTG4-based Data Processing Pipeline -- Workshop on Parallel Systems and Algorithms (PASA) -- Accelerating Real-Time Applications with Predictable Work-Stealing. 330 $aThis book constitutes the proceedings of the 33rd International Conference on Architecture of Computing Systems, ARCS 2020, held in Aachen, Germany, in May 2020.* The 12 full papers in this volume were carefully reviewed and selected from 33 submissions. 6 workshop papers are also included. ARCS has always been a conference attracting leading-edge research outcomes in Computer Architecture and Operating Systems, including a wide spectrum of topics ranging from embedded and real-time systems all the way to large-scale and parallel systems. The selected papers focus on concepts and tools for incorporating self-adaptation and self-organization mechanisms in high-performance computing systems. This includes upcoming approaches for runtime modifications at various abstraction levels, ranging from hardware changes to goal changes and their impact on architectures, technologies, and languages. *The conference was canceled due to the COVID-19 pandemic. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v12155 606 $aComputer networks 606 $aComputer systems 606 $aMicroprocessors 606 $aComputer architecture 606 $aComputer input-output equipment 606 $aComputer Communication Networks 606 $aComputer System Implementation 606 $aProcessor Architectures 606 $aInput/Output and Data Communications 615 0$aComputer networks. 615 0$aComputer systems. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 0$aComputer input-output equipment. 615 14$aComputer Communication Networks. 615 24$aComputer System Implementation. 615 24$aProcessor Architectures. 615 24$aInput/Output and Data Communications. 676 $a004.22 702 $aBrinkmann$b André$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aKarl$b Wolfgang$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aLankes$b Stefan$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aTomforde$b Sven$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aPionteck$b Thilo$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aTrinitis$b Carsten$4edt$4http://id.loc.gov/vocabulary/relators/edt 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a996418307303316 996 $aArchitecture of Computing Systems ? ARCS 2020$91990837 997 $aUNISA