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010   $a3-030-43243-2
024 7 $a10.1007/978-3-030-43243-0
035   $a(CKB)4100000011273674
035   $a(MiAaPQ)EBC6287344
035   $a(DE-He213)978-3-030-43243-0
035   $a(PPN)248394509
035   $a(EXLCZ)994100000011273674
100   $a20200509d2020      u|             0
101 0 $aeng
135   $aurcnu||||||||
181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 12$aA Pipelined Multi-Core Machine with Operating System Support$b[electronic resource] $eHardware Implementation and Correctness Proof /$fby Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul
205   $a1st ed. 2020.
210  1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2020.
215   $a1 online resource (634 pages)
225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v9999
311   $a3-030-43242-4 
327   $aIntroductory material -- on hierarchical hardware design -- hardware library -- basic processor design -- pipelining -- cache memory systems -- interrupt mechanism -- self modification, instruction buffer and nondeterministic ISA -- memory management units -- store buffers -- multi-core processors -- advanced programmable interrupt controllers (APICs) -- adding a disk -- I/O apic.
330   $aThis work is building on results from the book named ?A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness? by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014. It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features: ? MIPS instruction set architecture (ISA) for application and for system programming ? cache coherent memory system ? store buffers in front of the data caches ? interrupts and exceptions ? memory management units (MMUs) ? pipelined processors: the classical five-stage pipeline is extended by two pipeline stages for address translation ? local interrupt controller (ICs) supporting inter-processor interrupts (IPIs) ? I/O-interrupt controller and a disk .
410  0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v9999
606   $aComputer programming
606   $aComputer engineering
606   $aComputer networks
606   $aMicroprogramming
606   $aComputer input-output equipment
606   $aLogic programming
606   $aComputer science
606   $aProgramming Techniques
606   $aComputer Engineering and Networks
606   $aControl Structures and Microprogramming
606   $aInput/Output and Data Communications
606   $aLogic in AI
606   $aTheory of Computation
615  0$aComputer programming.
615  0$aComputer engineering.
615  0$aComputer networks.
615  0$aMicroprogramming.
615  0$aComputer input-output equipment.
615  0$aLogic programming.
615  0$aComputer science.
615 14$aProgramming Techniques.
615 24$aComputer Engineering and Networks.
615 24$aControl Structures and Microprogramming.
615 24$aInput/Output and Data Communications.
615 24$aLogic in AI.
615 24$aTheory of Computation.
676   $a005.434
700   $aLutsyk$b Petro$4aut$4http://id.loc.gov/vocabulary/relators/aut$0883073
702   $aOberhauser$b Jonas$4aut$4http://id.loc.gov/vocabulary/relators/aut
702   $aPaul$b Wolfgang J$4aut$4http://id.loc.gov/vocabulary/relators/aut
801  0$bMiAaPQ
801  1$bMiAaPQ
801  2$bMiAaPQ
906   $aBOOK
912   $a996418302503316
996   $aA Pipelined Multi-Core Machine with Operating System Support$91972560
997   $aUNISA