LEADER 00849oam 2200193z- 450 001 996397243703316 005 20200818211111.0 035 $a(CKB)4940000000055302 035 $a(EEBO)2273355720 035 $a(EXLCZ)994940000000055302 100 $a20191209c1677uuuu -u- - 101 0 $aeng 200 14$aThe novum organum of Sir Francis Bacon, Baron of Verulam, Viscount St. Albans, epitomiz'd for a clearer understanding of his natural history translated and taken out of the Latine by M.D 210 $cPrinted for Thomas Lee ..$aEngland 700 $aBacon$b Francis$0159133 906 $aBOOK 912 $a996397243703316 996 $aThe novum organum of Sir Francis Bacon, Baron of Verulam, Viscount St. Albans, epitomiz'd for a clearer understanding of his natural history translated and taken out of the Latine by M.D$92394459 997 $aUNISA LEADER 09652nam 22008415 450 001 9910768457503321 005 20251116234224.0 010 $a3-540-44687-7 024 7 $a10.1007/3-540-44687-7 035 $a(CKB)1000000000211626 035 $a(SSID)ssj0000323123 035 $a(PQKBManifestationID)11277788 035 $a(PQKBTitleCode)TC0000323123 035 $a(PQKBWorkID)10296894 035 $a(PQKB)11222564 035 $a(DE-He213)978-3-540-44687-3 035 $a(MiAaPQ)EBC3072592 035 $a(PPN)155190296 035 $a(BIP)13627155 035 $a(BIP)7351709 035 $a(EXLCZ)991000000000211626 100 $a20121227d2001 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aField-Programmable Logic and Applications $e11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings /$fedited by Gordon Brebner, Roger Woods 205 $a1st ed. 2001. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2001. 215 $a1 online resource (XV, 665 p.) 225 1 $aLecture Notes in Computer Science,$x0302-9743 ;$v2147 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a3-540-42499-7 320 $aIncludes bibliographical references at the end of each chapters and index. 327 $aInvited Keynote 1 -- Technology Trends and Adaptive Computing -- Architectural Frameworks -- Prototyping Framework for Reconfigurable Processors -- An Emulator for Exploring RaPiD Configurable Computing Architectures -- Place and Route 1 -- A New Placement Method for Direct Mapping into LUT-Based FPGAs -- fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits -- Architecture -- Macrocell Architectures for Product Term Embedded Memory Arrays -- Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs -- Memory Synthesis for FPGA-Based Reconfigurable Computers -- DSP 1 -- Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic -- Implementation of (Normalised) RLS Lattice on Virtex -- Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing -- Synthesis -- Static Profile-Driven Compilation for FPGAs -- Synthesizing RTL Hardware from Java Byte Codes -- PuMA++: From Behavioral Specification to Multi-FPGA-Prototype -- Encryption -- Secure Configuration of Field Programmable Gate Arrays -- Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm -- JBits? Implementations of the Advanced Encryption Standard (Rijndael) -- Runtime Recon.guration 1 -- Task-Parallel Programming of Reconfigurable Systems -- Chip-Based Reconfigurable Task Management -- Configuration Caching and Swapping -- Graphics and Vision -- Multiple Stereo Matching Using an Extended Architecture -- Implementation of a NURBS to Bézier Conversor with Constant Latency -- Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems -- Invited Keynote 2 -- Processing Models for the Next Generation Network -- Place and Route 2 -- Tightly Integrated Placement and Routing for FPGAs -- Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays -- Networking -- Reconfigurable Router Modules Using Network Protocol Wrappers -- Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware -- Processor Interaction -- The MOLEN ??-Coded Processor -- Run-Time Optimized Reconfiguration Using Instruction Forecasting -- CRISP: A Template for Reconfigurable Instruction Set Processors -- Applications -- Evaluation of an FPGA Implementation of the Discrete Element Method -- Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers -- A Reconfigurable Embedded Input Device for Kinetically Challenged Persons -- Methodology 1 -- Bubble Partitioning for LUT-Based Sequential Circuits -- Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits -- Placing, Routing, and Editing Virtual FPGAs -- DSP 2 -- Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver -- A Music Synthesizer on FPGA -- Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders -- Loops and Systolic -- Loop Tiling for Reconfigurable Accelerators -- The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems -- A n-Bit Reconfigurable Scalar Quantiser -- Image Processing -- Real Time Morphological Image Contrast Enhancement in Virtex FPGA -- Demonstrating Real-time JPEG Image Compression-Decompression using Standard Component IP Cores on a Programmable Logic based Platform for DSP and Image Processing -- Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware -- Invited Keynote 3 -- The Evolution of Programmable Logic: Past, Present, and Future Predictions -- Runtime Reconfiguration 2 -- Dynamically Reconfigurable Cores -- Reconfigurable Breakpoints for Co-debug -- Faults -- Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification -- FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits -- Methodology 2 -- A Generic Library for Adaptive Computing Environments -- Generative Development System for FPGA essors with Active Components -- Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines -- System Level Tools for DSP in FPGAs -- Arithmetic -- Parameterized Function Evaluation for FPGAs -- Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures -- A Digit-Serial Structure for Reconfigurable Multipliers -- FPGA Resource Reduction Through Truncated Multiplication -- Short Papers 1 -- Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures -- An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars -- Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach -- An Approach to Real-Time Visualization of PIV Method with FPGA -- FPGA-Based Discrete Wavelet Transforms System -- X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor -- Arithmetic Operation Oriented Reconfigurable Chip: RHW -- Short Papers 2 -- Initial Analysis of the Proteus Architecture -- Building Asynchronous Circuits with JBits -- Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux -- A Reconfigurable Approach to Packet Filtering -- FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding -- A Data Re-use Based Compiler Optimization for FPGAs -- Dijkstra?s Shortest Path Routing Algorithm in Reconfigurable Hardware -- A System on Chip for Power Line Communications According to European Home Systems Specifications. 330 $aThis book constitutes the refereed proceedings of the 11th International Conference on Field-Programmable Logic and Application, FPL 2001, held in Belfast, Northern Ireland, UK, in August 2001.The 56 revised full papers and 15 short papers presented were carefully reviewed and selected from a total of 117 submissions. The book offers topical sections on architectural framework, place and route, architecture, DSP, synthesis, encryption, runtime reconfiguration, graphics and vision, networking, processor interaction, applications, methodology, loops and systolic, image processing, faults, and arithmetic. 410 0$aLecture Notes in Computer Science,$x0302-9743 ;$v2147 606 $aComputer architecture 606 $aSoftware engineering 606 $aComputer networks 606 $aLogic design 606 $aMicroprocessors 606 $aComputer-aided engineering 606 $aComputer System Implementation$3https://scigraph.springernature.com/ontologies/product-market-codes/I13057 606 $aSoftware Engineering/Programming and Operating Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/I14002 606 $aComputer Communication Networks$3https://scigraph.springernature.com/ontologies/product-market-codes/I13022 606 $aLogic Design$3https://scigraph.springernature.com/ontologies/product-market-codes/I12050 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 606 $aComputer-Aided Engineering (CAD, CAE) and Design$3https://scigraph.springernature.com/ontologies/product-market-codes/I23044 615 0$aComputer architecture. 615 0$aSoftware engineering. 615 0$aComputer networks. 615 0$aLogic design. 615 0$aMicroprocessors. 615 0$aComputer-aided engineering. 615 14$aComputer System Implementation. 615 24$aSoftware Engineering/Programming and Operating Systems. 615 24$aComputer Communication Networks. 615 24$aLogic Design. 615 24$aProcessor Architectures. 615 24$aComputer-Aided Engineering (CAD, CAE) and Design. 676 $a621.39/5 702 $aBrebner$b Gordon$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aWoods$b Roger$4edt$4http://id.loc.gov/vocabulary/relators/edt 712 12$aInternational Conference on Field-Programmable Logic and Applications 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910768457503321 996 $aField-programmable logic and applications$92106948 997 $aUNINA