LEADER 01331nam 2200385 n 450 001 996390574203316 005 20221214190403.0 035 $a(CKB)4940000000102455 035 $a(EEBO)2240886417 035 $a(UnM)99842458e 035 $a(UnM)99842458 035 $a(EXLCZ)994940000000102455 100 $a19910509d1566 uy | 101 0 $adut 135 $aurbn#|||a|bb| 200 13$aDe kleyne catechismus$b[electronic resource] $ekinder of berichtleere der Duyscher ghemeynte to Londen. /$fGhemaeckt door Marten Micron 210 $aGhedruckt to Londen $cby Ian Daye$dden twelften Septembris. 1566 215 $a47 leaves 300 $aAdapted by Micronius from: ?aski, Jan. De catechismus, oft kinder leere, diemen te Londen, is ghebruyckende. 300 $aText in black letter. 300 $aSome print show-through. 300 $aReproduction of the original in the Bodleian Library. 330 $aeebo-0014 606 $aCatechisms, Dutch$vEarly works to 1800 615 0$aCatechisms, Dutch 700 $a?aski$b Jan$f1499-1560.$0225761 701 $aMicronius$b Marten$f1523-1559.$0896310 801 0$bCu-RivES 801 1$bCu-RivES 801 2$bCStRLIN 801 2$bWaOLN 906 $aBOOK 912 $a996390574203316 996 $aDe kleyne catechismus$92365483 997 $aUNISA LEADER 05338nam 2200673Ia 450 001 9910784350603321 005 20230120004349.0 010 $a1-281-03935-7 010 $a9786611039356 010 $a0-08-055143-2 035 $a(CKB)1000000000349707 035 $a(EBL)312850 035 $a(OCoLC)476101324 035 $a(SSID)ssj0000136204 035 $a(PQKBManifestationID)11150269 035 $a(PQKBTitleCode)TC0000136204 035 $a(PQKBWorkID)10083736 035 $a(PQKB)11034288 035 $a(Au-PeEL)EBL312850 035 $a(CaPaEBR)ebr10190357 035 $a(CaONFJC)MIL103935 035 $a(CaSebORM)9780750685344 035 $a(MiAaPQ)EBC312850 035 $a(EXLCZ)991000000000349707 100 $a20070911d2007 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 14$aThe definitive guide to the ARM Cortex-M3$b[electronic resource] /$fJoseph Yiu 205 $a1st edition 210 $aAmsterdam ;$aBoston $cNewnes$dc2007 215 $a1 online resource (380 p.) 225 1 $aEmbedded technology series 300 $aIncludes bibliographical references (p. xix) and index. 311 $a0-7506-8534-4 327 $aFront Cover; The Definitive Guide to the ARM Cortex-M3; Copyright Page; Table of Contents; Foreword; Preface; Acknowledgments; Terms and Abbreviations; Conventions; References; Chapter 1 - Introduction; What Is the ARM Cortex-M3 Processor?; Background of ARM and ARM Architecture; A Brief History; Architecture Versions; Processor Naming; Instruction Set Development; The Thumb-2 Instruction Set Architecture (ISA); Cortex-M3 Processor Applications; Organization of This Book; Further Readings; Chapter 2 - Overview of the Cortex-M3; Fundamentals; Registers; R0 to R12: General-Purpose Registers 327 $aR13: Stack PointersR14: The Link Register; R15: The Program Counter; Special Registers; Operation Modes; The Built-In Nested Vectored Interrupt Controller; Nested Interrupt Support; Vectored Interrupt Support; Dynamic Priority Changes Support; Reduction of Interrupt Latency; Interrupt Masking; The Memory Map; The Bus Interface; The Memory Protection Unit; The Instruction Set; Interrupts and Exceptions; Debugging Support; Characteristics Summary; High Performance; Advanced Interrupt-Handling Features; Low Power Consumption; System Features; Debug Supports; Chapter 3 - Cortex-M3 Basics 327 $aRegistersGeneral-Purpose Registers R0-R7; General-Purpose Registers R8-R12; Stack Pointer R13; Link Register R14; Program Counter R15; Special Registers; Program Status Registers (PSRs); PRIMASK, FAULTMASK, and BASEPRI Registers; The Control Register; Operation Mode; Exceptions and Interrupts; Vector Tables; Stack Memory Operations; Basic Operations of the Stack; Cortex-M3 Stack Implementation; The Two-Stack Model in the Cortex-M3; Reset Sequence; Chapter 4 - Instruction Sets; Assembly Basics; Assembler Language: Basic Syntax; Assembler Language: Use of Suffixes 327 $aAssembler Language: Unified Assembler LanguageInstruction List; Unsupported Instructions; Instruction Descriptions; Assembler Language: Moving Data; LDR and ADR Pseudo Instructions; Assembler Language: Processing Data; Assembler Language: Call and Unconditional Branch; Assembler Language: Decisions and Conditional Branches; Assembler Language: Combined Compare and Conditional Branch; Assembler Language: Conditional Branches Using IT Instructions; Assembler Language: Instruction Barrier and Memory Barrier Instructions; Assembly Language: Saturation Operations 327 $aSeveral Useful Instructions in the Cortex-M3MSR and MRS; IF-THEN; CBZ and CBNZ; SDIV and UDIV; REV, REVH, and REVSH; RBIT; SXTB, SXTH, UXTB, and UXTH; BFC and BFI; UBFX and SBFX; LDRD and STRD; TBB and TBH; Chapter 5 - Memory Systems; Memory System Features Overview; Memory Maps; Memory Access Attributes; Default Memory Access Permissions; Bit-Band Operations; Advantages of Bit-Band Operations; Bit-Band Operation of Different Data Sizes; Bit-Band Operations in C Programs; Unaligned Transfers; Exclusive Accesses; Endian Mode; Chapter 6 - Cortex-M3 Implementation Overview; The Pipeline 327 $aA Detailed Block Diagram 330 $aThis user's guide does far more than simply outline the ARM Cortex-M3 CPU features; it explains step-by-step how to program and implement the processor in real-world designs. It teaches readers how to utilize the complete and thumb instruction sets in order to obtain the best functionality, efficiency, and reuseability. The author, an ARM engineer who helped develop the core, provides many examples and diagrams that aid understanding. Quick reference appendices make locating specific details a snap! Whole chapters are dedicated to: Debugging using the new CoreSight technologyMi 410 0$aEmbedded technology series. 606 $aEmbedded computer systems 606 $aMicroprocessors 615 0$aEmbedded computer systems. 615 0$aMicroprocessors. 676 $a004.16 676 $a004.256 700 $aYiu$b Joseph$01102604 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910784350603321 996 $aThe definitive guide to the ARM Cortex-M3$93744875 997 $aUNINA