LEADER 01401nam 2200325Ia 450 001 996397513503316 005 20200818212049.0 035 $a(CKB)4940000000060190 035 $a(EEBO)2264174307 035 $a(OCoLC)ocm19507216e 035 $a(OCoLC)19507216 035 $a(EXLCZ)994940000000060190 100 $a19890407d1662 uy | 101 0 $aeng 135 $aurbn||||a|bb| 200 10$aArticles of visitation & enquiry concerning matters ecclesiastical$b[electronic resource] $eexhibited to the ministers, church-wardens, and side-men of every parish within the diocese of Saint Asaph, in the primary episcopal visitation of the Right Reverend Father in God, George, by divine providence, Lord Bishop of Saint Asaph 210 $aLondon $cPrinted for T. Garthwait ...$dM.DC.LXII. [1662] 215 $a[2], 10 p 300 $aIncludes marginal notes. 300 $aCopy at reel 324:1 is eighth title in a collection of visitation articles, bound and filmed together. 300 $aReproduction of original in the Bodleian Library. 330 $aeebo-0014 606 $aVisitations, Ecclesiastical$zEngland 615 0$aVisitations, Ecclesiastical 701 $aGriffith$b George$f1601-1666.$01013297 801 0$bEAH 906 $aBOOK 912 $a996397513503316 996 $aArticles of visitation & enquiry concerning matters ecclesiastical$92366909 997 $aUNISA LEADER 02346nam 2200373 450 001 996280849703316 005 20231207080854.0 010 $a1-55937-136-6 024 7 $a10.1109/IEEESTD.1991.101070 035 $a(CKB)3780000000089909 035 $a(NjHacI)993780000000089909 035 $a(EXLCZ)993780000000089909 100 $a20231207d1991 uy 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aIEEE Std 1005-1991 $eIEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays /$fInstitute of Electrical and Electronics Engineers 210 1$aNew York, NY, USA :$cIEEE,$d1991. 215 $a1 online resource (41 pages) 330 $aAn introduction to the physics unique to this type of memory and an overview of typical array architectures are presented. The variations on the basic floating gate nonvolatile cell structure that have been used in commercially available devices are described. The various reliability considerations involved in these devices are explored. Retention and endurance failures and the interaction between endurance, retention, and standard semiconductor failure mechanisms in determining the device failure rate are covered. How to specify and perform engineering verification of retention of data stored in the arrays is described. Effects that limit the endurance of the arrays are discussed. The specification and engineering verification of endurance are described. The more common features incorporated into the arrays and methods for testing these complex products efficiently are addressed. The effects that various forms of ionizing radiation may have on floating gate arrays and approaches to test for these effects are covered. The use of floating gate cells in nonmemory applications is briefly considered. 517 $aIEEE Std 1005-1991 606 $aIntegrated circuits$xVery large scale integration$xTesting 606 $aSemiconductor storage devices 615 0$aIntegrated circuits$xVery large scale integration$xTesting. 615 0$aSemiconductor storage devices. 676 $a621.3973 801 0$bNjHacI 801 1$bNjHacl 906 $aDOCUMENT 912 $a996280849703316 996 $aIEEE Std 1005-1991$93646578 997 $aUNISA